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Atmel claims 'lowest-power' 32bit flash MCUs with Ethernet, USB OTG

Posted: 10 Apr 2007 ?? ?Print Version ?Bookmark and Share

Keywords:32bit flash MCU? flash memory? embedded 10/100 Ethernet?

32bit flash MCUs from Atmel

Atmel Corp. has announced what it claims is the industry's lowest power 32bit flash MCUs. Based on the company's AVR 32 UC core, the UC3A series has 512Kbytes of flash and features an embedded 10/100 Ethernet MAC, a full-speed USB 2.0 with OTG, and an SRAM/SDRAM external bus interface.

The AT32UC3A0512 and AT32UC3A1512, the first devices in the new series, deliver 80 Dhrystone MIPS (DMIPS) at 66MHz and consume 40mA at 3.3V. The 1.65mW/DMIPS power consumption outperforms other architectures with similar features by a ratio of up to 4X, the company said. The new MCUs target networking and PC-centric embedded applications and are suitable for portable devices.

3-stage pipeline Harvard architecture
The AVR32 UC core uses a three-stage pipeline Harvard architecture designed to optimize instruction fetches from on-chip flash memory. This core integrates single-cycle read/write SRAM with a direct interface to the CPU that bypasses the system bus to achieve fast execution, cycle determinism and low power consumption. It shares the same ISA as its AVR32 AP parent, with over 220 modeless instructions available as 16bit compact and 32bit extended instructions. The ISA features atomic bit manipulation to control on-chip peripherals and GPIOs and fixed point DSP arithmetic such as single cycle fractional saturated multiply-and-accumulate. An event handling system supports events such as prioritized interrupts, non-maskable interrupt and internal exceptions with a maximum interrupt latency of 16 clock cycles.

The AVR32 UC3A series incorporates many of the same peripherals as Atmel's ARM-based MCUs including the peripheral DMA controller, multilayer high-speed bus architecture, 10bit ADC, two SPIs, SSC, two-wire interface (I?C-compatible), four UARTs, three general-purpose timers, seven pulse width modulators and a full set of supervisory functions.

The 10/100Mbps IEEE 802.3-compliant Ethernet (MAC) allows designing networked embedded systems that communicate over IP stacks. The USB 2.0 full speed interface provides a means to communicate with today's PC architecture through various USB classes such as HID for serial data communication or Mass-Storage for larger bulked data transfers. The OTG capability of the UC3A USB peripheral gives further integration opportunity in a PC-centric environment with the support of standard USB devices such as USB flash disk, pointing devices or printers.

16MB addressable physical memory
The EBI extends the addressable physical memory to 16Mbytes. Its non-multiplexed 16bit data bus can interface to high-density external SRAM, SDRAM, ROM, flash devices and memory-mapped devices such as LCDs or FPGAs.

UC3A series MCUs have a six-layer high-speed bus matrix that enables bus masters peripherals to concurrently access any bus slave at a maximum speed of 264MBps at 66MHz. The bus masters are the AVR32 UC core data and instruction interfaces, 15-channel peripheral DMA controller and several high-speed peripherals such as the Ethernet MAC and USB. The bus slaves are the on-chip SRAM and flash memories, USB, the two peripheral bus bridges and the EBI.

The AT32UC3A0512, with EBI, is available in a 144-pin QFP package and the AT32UC3A1512, without EBI, is available in a 100-pin QFP package. Pricing starts at $8.16 and $7.43 for 10,000-unit quantities, respectively.




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