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TSMC commences 45nm process

Posted: 11 Apr 2007 ?? ?Print Version ?Bookmark and Share

Keywords:45nm process technology? TSMC foundry customers? 45nm logic chips?

Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) has rolled out its 45nm process technology for foundry customers, with plans to enter production as early as September 2007.

As reported,TSMC originally tipped the process last year. The new 45nm process combines 193nm immersion photolithography, strained silicon and ultra low-k inter-metal dielectric material.

TSMC's 45nm low power process provides twice the density of 65nm with lower power and manufacturing cost per die. Its 45nm general-purpose and high-performance process provides more than double the density and a greater than 30 percent speed enhancement over the previous generation at similar leakage power.

With a high-density 6T SRAM cell, more than 500 million transistors will fit into a 70mm? die area. In addition, the 45nm logic family includes a low-power triple gate oxide (LPG) option. All three processes offer multiple threshold voltage (Vt) core devices and 1.8-, 2.5- and 3.3V I/O options to meet different product requirements.

TSMC has delivered functional chips from its 45nm multiproject wafer program, dubbed Cybershuttle.

- Mark LaPedus
EE Times

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