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SPI packs DSPs with stream processing

Posted: 16 Apr 2007 ?? ?Print Version ?Bookmark and Share

Keywords:high-performance signal-processing applications? DSP for video and image processing?

Stream Processors Inc. (SPI), a fabless chip vendor built on a foundation of MIT and Stanford research, emerges from stealth mode to introduce two parts that embody what the company calls a fundamentally new architecture and the first commercial application of stream processing for DSPs.

SPI has been sampling the initial Storm-1 products since late 2006, and executives say the startup has been engaged with a customer for nearly a year. The devices target such high-performance signal-processing applications as video and image processing. They are the 8-lane SP8-G80, which can execute 80 giga-operations per second, and the 16-lane SP16-G160, which can execute 160 giga-operations per second, SPI said. The devices are said to deliver a more than tenfold cost/performance advantage over conventional DSPs.

The company presented a paper on its architecture at this year's International Solid-State Circuits Conference.

SPI describes stream processing as a programming model and processor architecture designed for parallel processing with compiler-managed hierarchy. The architecture achieves high performance through data-parallel processing in kernel functions. It is said to be "best-suited" for applications that are compute-intensive, involve data parallelism and exhibit data locality, according to SPI. Examples include A/V codecs, analytics, and image and graphics processing.

Sixteen-lane SP16-G160 delivers single flow of execution and simpler design than partitioned multicore approach. (Click to view full image)

Tim Southgate, VP of software engineering for SPI, said the programmable processor can also be used for other applications. Bengt Christensson, VP of business development, said the SPI road map calls for targeting more high-performance applications and adding products for use in the consumer space.

The executives said the SPI architecture does not include hardware caches, which can dominate the silicon area of traditional DSPs. Instead, an SPI device relies on lane register files to store I/O streams for each of its multiple lanes. Maintaining data locality enables the architecture to maximize both efficiency and bandwidth, Southgate said.

Rush to parallelism
Jeff Bier, president of Berkeley Design Technology Inc., an independent analysis firm, cited a rush toward highly parallel architectures. The consensus is that greater parallelism is the "best" way to get higher levels of performance while maintaining reasonable cost and power consumption, Bier said.

Approaches to greater parallelism differ, he said. SPI targets data-level parallelism, whereas others are more focused on task-level parallelism. "The upshot is that SPI can present programmers with a much simpler programming model than can vendors who are focused on task-level parallelism," Bier said.

A key feature of the SPI devices is an ANSI C programming environment. The company offers a functional debugger library, a target simulator and a Storm SP16 development kit.

Other multicore approaches run different tasks on different processors, creating programming complexity. SPI's approach runs one task at a time, but with massive levels of parallelism to accelerate key tasks, Bier said. SPI's challenge is to demonstrate that targeted applications "map well" to the SPI approach and can make efficient use of the available processing resources, he said.

The good news for SPI, according to Bier, is that the video- and image-processing applications the company is chasing have substantial amounts of data parallelism. "Certain types of applications, such as scaling video frames from one resolution to another, would be a perfect match," he said. "But even within video applications, there are other kinds of tasks where it's not so obvious how you make use of this type of architecture."

The SP8-G80 and SP16-G160 are priced at $59 and $99 per unit, respectively, in 10,000-unit quantities. Each operates at 500MHz and includes 32-, 64- or 128bits of DDR2 DRAM.

Taiwan Semiconductor Manufacturing Co. Ltd is manufacturing the devices in a 130nm process. SPI plans to have its second-generation devices built in 65nm technology, Christensson said.

SPI was founded in 2004. Chairman and CTO William Dally, who also chairs the computer science department at Stanford University, has led research on stream processing at Stanford and MIT.

- Dylan McGrath
EE Times

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