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Equivalence checker supports FPGA optimizations

Posted: 16 Apr 2007 ?? ?Print Version ?Bookmark and Share

Keywords:sequential optimizations? FPGA equivalence checking? combinatorial ASIC logic?

To run formal equivalence checking on FPGAs today, designers typically have to turn off sequential optimizations made by synthesis tools. Startup OneSpin Solutions GmbH introduced a solution that makes FPGA equivalence checking practical by supporting those optimizations.

While equivalence checking is widely used for ASIC designs, its use for complex FPGAs lags behind, due in part to the difficulty of handling common FPGA synthesis optimizations such as retiming. "FPGAs are much more aggressively optimized than ASICs," said Wolfram Buettner, managing director and CTO of OneSpin.

In combinatorial ASIC logic, Buettner said, registers are usually the same before and after synthesis, and only the logic between them is optimized. But with FPGAs, he said, registers may no longer correspond after synthesis because some may be optimized away. Thus, proving equivalency for logic alone isn't enough. It's also necessary to verify sequential changes involving registers.

OneSpin is a spin-off from Infineon Technologies' circuit verification environment unit. The company rolled out last year its 360 module verifier, which detects functional errors in digital modules and intellectual property. It also launched the 360 equivalence checker (EC) for ASIC design.

Equivalence checking and verification of sequential optimizations are supported.

The new 360 EC-FPGA provides all the capabilities of the ASIC checker, including support for sequential optimizations commonly used with FPGAs. It verifies the functional equivalence of RTL and postsynthesis netlists, as well as gate-level and postrouting FPGA netlists. It can be complemented by the 360 module verifier, but doesn't require its use.

Buettner noted that the 360 EC-FPGA is aimed at very complex FPGA designs, perhaps the top 10 percent of the overall FPGA design market. Designers in this sector need equivalence checking, he said, but are currently forced to turn off synthesis optimizations to use it.

The product handles all current FPGA synthesis optimizations, Buettner said. It supports Altera and Xilinx FPGAs, and works with the Synplicity Synplify Pro and Altera Quartus II synthesis tools.

OneSpin claims the 360 EC-FPGA's typical verification runtimes for complex designs are around 10-30 percent of the time required for synthesis, placement and routing.

Peter Feist, OneSpin's new president and CEO, noted that 360 EC-FPGA does not require extensive scripting or side files. Thus, he said, it allows the FPGA design flow to retain a high level of automation. The tool takes in pre- and postsynthesis netlists and compares them. It's a "straightforward, pushbutton" operation, he said.

The 360 EC-FPGA solution is available now for $137,500, which is high for an FPGA design tool, but Buettner said high-end users will recognize the value of 360 EC-FPGA and be able to calculate the return on investment.

OneSpin has thus far sold mostly in Europe, but the company opened an office in California in December.

- Richard Goering
EE Times

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