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Optimize power in embedded DSP designs

Posted: 16 Apr 2007 ?? ?Print Version ?Bookmark and Share

Keywords:power consumption? embedded DSP design? power consumption in DSP design?

Optimizing power consumption is an important design goal for DSP-based systems, but it is a goal that is often difficult to achieve. Today, DSP-based equipment often combines applications that were previously separate, with each application having multiple operating modes. Developing a power profile for such a device is very difficult. Designers need the best information available, techniques and tools that can help them optimize power consumption within the specific application.

Fortunately, DSP chip design and manufacturing processes have developed more advanced methods for reducing power consumption. On-chip power-optimization techniques now offer more granular control, more power-saving modes and complete information about processor power consumption than ever before. Newer DSP development tools give designers more insight into how their systems consume power and provide techniques for lowering power consumption via on-chip hardware.

Profiles, chip resources
The first step to reduce power in any system is to understand how the system is used and how that usage affects power consumption. For instance, a cellphone spends a lot of time waiting for a call, but relatively little time during the call. An MP3 player, on the other hand, is normally either on and in active operation, or off. Other systemsline-powered and portablehave different profiles of standby and active operation.

Understanding this profile can help the designer choose a power-efficient processor, since the fundamental CMOS technology of a DSP can greatly affect power consumption in a specific type of application. Advanced CMOS processes are based on high-performance transistors that run at extremely low voltages. Depending on the intended application, the transistors can be tailored either to minimize power consumption by clamping quiescent current or to maximize performance, although with slightly greater current leakage. DSPs designed for applications with long standby times keep quiescent current to a minimum with low-leakage transistors, while DSPs designed for high-performance applications favor faster-switching transistors.

System usage also involves the responsiveness of the system to events, and thus, the latency when circuitry is powered on. Some delay is expected on initial power-up, and a lesser delay is acceptable when a system wakes from a standby mode. But users generally expect immediate response from a system that is in active operation so that on-chip functions can't be too deeply asleep at these times. Two considerations enter here: first, some functions can be shut down more completely than others, but also during active operation. Second, the more granularity the processor offers in controlling its power modes, the more the designer can tailor power consumption to the operating profile of the system.

Power-efficient DSP chip designs consider these matters by creating power domains that enable the application to disconnect the clock inputs to functions not in use. Just as a processing core can enter a sleep mode, so can peripherals and memory blocks be put to sleep until needed. The transistors in the unclocked functions lose no power except for quiescent current, and the wake-up delay required for resuming the clock is minimal. As system designers consider the usage profiles of their products, they also need to consider how much control the DSP gives them or handles automatically over clocking individual functions.

Power-conscious design techniques help the DSP developer take full advantage of a valid power estimate. At the system level, the designer should select components carefully and keep their number as low as possible. In addition, the designer should consider which unused components can be powered down at times, especially during standby operation. Use of board-level memory is also a power drain, since it has to energize both memory chips and board traces.

Whenever possible, the application should use the DSP's internal memory, keeping high-bandwidth memory on-chip and reserving external memory for low-speed, occasional access. Off-chip memory also serves well for booting, but should be powered down after startup. Software should be optimized for performance to reduce the code's footprint in memory and the number of instruction fetches. Tighter code makes better use of the cache and internal instruction buffers. Since it generally runs faster, it reduces the system's time in active mode.

The most device-specific power reductions take advantage of the DSP's built-in hardware capabilities. From startup on, the application can idle domains that are not in use, limiting peripheral power consumption to only the I/Os that are needed at a given time. Normally, the application controls the domains directly at boot time, while later on, the DSP core can run a background loop that checks for functions not needed and turns them off. If the application uses these techniques, the chip's sleep modes can minimize the power drains of the core and chip domains during idle times.

The DSP core voltage and frequency (V/F) can be scaled at boot time if the total performance required does not equal the full capabilities of the device. V/F scaling can also be dynamically invoked during runtime if, say, the system alternates among applications that have different performance loads. For V/F scaling, the design has to provide external control of the DSP's supply voltage and software control built into the background loop. Since frequency scaling slows the core's operation, the designer should consider the timing of dependent operations in designing the application.

Simplify system analysis
Dealing with techniques effectively requires tools designed for power management. Paralleling other areas of DSP tool development, power optimization tools seek to provide visibility and ease-of-use to help simplify system analysis and speed time-to-market.

The tools work with the DSP's embedded and RTOS power-management techniques while providing test features such as meters, scope waveforms, channel calibration, test code and event triggering. With these capabilities in hand, the designer has a feedback mechanism that enables evaluation of how alternate implementations affect power consumption.

To optimize power consumption, a designer needs to understand the power profile of the system, then reference an information resource that considers all the major system functions in deriving a power estimate. DSPs based on power-efficient CMOS processes integrate hardware techniques such as granularly defined low-power modes, and voltage and frequency scaling. APIs make these techniques readily available to the application for control through the RTOS, and test tools help the designer evaluate different implementations for power consumption. With all of these resources available, developers have every reason to design for power from the very beginning of the development cycle.

- Jim Patterson
Group Technical Staff Member

- John Dixon
Worldwide C5000 Platform Marketing Manager, Texas Instruments Inc.

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