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Synthesis solution boosts IC performance

Posted: 24 Apr 2007 ?? ?Print Version ?Bookmark and Share

Keywords:topographical technology? synthesis solution? IC design?

Synopsys Inc. has released the Design Compiler 2007 synthesis solution, which extends topographical technology to accelerate design closure for designs utilizing advanced low-power and test techniques, boosting designer productivity and IC performance.

Topographical technology allows designers to accurately estimate a chip's power consumption during synthesis and address any power issues early in the design cycle. It also supports new test compression technology in Design Compiler 2007 to achieve high test quality while reducing test time and test data volume by more than 100 times.

In addition, the technology delivers tight correlation between performance results seen during synthesis and what is achieved after layout. This eliminates the need for time-consuming iterations between RTL synthesis and physical layout to achieve design closure. Design Compiler shares technologies and infrastructure with the GalaxyT Design Platform physical design solution to deliver a consistent and highly predictable RTL-to-GDSII path.

"Using topographical technology, the performance predictions made by synthesis correlated within 5 percent of physical implementation results," said Huang Tao, design manager at Hisilicon. "Design Compiler 2007 additionally reduced chip area by an average of 5 percent while meeting the aggressive performance targets of our telecom designs. Superior performance complemented by tight correlation to layout is exactly what our designers need to bring competitive products to market faster."

Design Compiler 2007 also includes several innovative synthesis technologies such as adaptive retiming and power-driven clock gating, to deliver an average 8 percent higher performance, 4 percent smaller area and 5 percent lower power consumption compared to the previous release. In addition, the Synopsys formality equivalence checking solution has been enhanced to verify these technologies, thereby allowing designers to achieve higher performance without sacrificing verification.

"In today's design environment, each design presents a unique set of implementation challenges that must be overcome to ensure predictable silicon success," said Antun Domic, senior VP and general manager, Synopsys implementation group. "The advanced technologies in Design Compiler 2007 are helping designers meet their toughest performance targets while achieving the fastest and most predictable path to silicon."

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