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Samsung develops 'first' all-DRAM stacked package using TSV tech

Posted: 25 Apr 2007 ?? ?Print Version ?Bookmark and Share

Keywords:DRAM memory package? WSP DRAM package? wafer processed package?

Samsung Electronics Co. Ltd claims to have developed the 'first' all-DRAM stacked memory package using 'through silicon via' (TSV) technology, which will result in memory packages that are faster, smaller and consume less power.

The wafer-level-processed stacked package (WSP) consists of four 512Mbit DDR2 DRAM chips that offer a combined 2Gbits of high density memory. Using the TSV-processed 2Gbit DRAMs, Samsung can create a 4Gbyte DIMM based on advanced WSP technology for the first time. Samsung's proprietary WSP technology not only reduces the overall package size, but also permits the chips to operate faster and use less power.

"The innovative TSV-based multichip package stacking technology offers next-generation packaging solution that will accommodate the ever-growing demand for smaller-sized, high-speed, high-density memory," said Tae-Gyeong Chung, VP, interconnect technology development team, memory division, Samsung. "In addition, the performance advancements achieved by our WSP technology can be used in many diverse combinations of semiconductor packaging, such as system-in-package solutions that combine logic with memory."

In today's MCPs, memory chips are connected by wire bonding, requiring vertical spacing between dies that is tens of microns deep. This wire bonding process also requires horizontal spacing on the package board hundreds of microns wide for the die-connecting wires. By contrast, Samsung's WSP technology forms laser-cut micron-sized holes that penetrate the silicon vertically to connect the memory circuits directly with a copper filling, eliminating the need for gaps of extra space and wires protruding beyond the sides of the dies. These advantages enable the WSP solution to offer a smaller footprint and thinner package.

Inside the new WSP, the TSV is housed within an aluminum pad to escape the performance-slow-down effect caused by the redistribution layer. Due to the complexity of DRAM stacking, this represented a much more difficult engineering feat than that accomplished with the first WSP, announced last year involving NAND flash dies.

There has been considerable concern that MCPs with high-speed memory chips with speed of 1.6Gbps next generation DRAM, would suffer from performance limitations when connected using current technologies. Samsung claims that its WSP technology resolves these concerns.

Moreover, as the back side of the wafer is ground away to make a thinner stack of multiple dies, the wafer has had a tendency to curve, creating physical distortion in the die. To address this concern in designing low-profile, high-density MCPs containing DRAM circuitry, Samsung's proprietary wafer-thinning technology, announced last year, has been applied to improve the thin-die-cutting process.

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