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The basics of HD H.264 and next-generation encoding

Posted: 01 May 2007 ?? ?Print Version ?Bookmark and Share

Keywords:MPEG2 H.264/ AVC? ASIC SoC codec? DSP H.264?

By Paul Greene, NVISION
?????Shubha Tuljapurkar, Telairity

Video compression is a complex, compute-intensive task with numerous filtering and matrix operations. Current MPEG2 video codec chips have built-in DSPs, or special VLIW engines, and some hard-coded functionality to compress video in real-time. However, as the industry moves to high definition (HD) encoding, there is six times as much data to process as standard definition (SD), and the H.264/ AVC compression standard is greater than five times as complex as MPEG2, due to the large number of compression tools and options in AVC that can be used to compress a superlative picture at half the bit rate of MPEG2.

Broadcast equipment manufacturers developing new encoding products have to address different application requirements including those for the rapidly emerging IPTV segment. Encoding solutions must not only deliver high video quality and a low bit rate, but they should also be adaptable to the feature needs of the quickly proliferating range of video platforms. There are several solutions available to meet the challenges of HD video encoding, including PC platforms, FPGAs, dedicated ASIC/SoC codecs, and DSPs. We discuss the benefits and costs of each of these solutions, and draw on Telairity's experience in developing its H.264 HD real-time encoders to highlight the importance of programmable architectures for encoding solutions that deliver long-haul viability.

PC platforms, FPGAs, SoCs and DSPs
One solution for HD processing that is appealing because of its ubiquity, and its increasing performance, is to use the PC platform and a combination of software and supplemental video hardware. However, since PC CPUs such as the Intel Pentium' or AMD Opteron' are designed for PC applications and not video processing, multiple dual or quad Intel/AMD processors are required to accomplish the task of encoding HD video. Specialized hardware for motion estimation, typically FPGAs, is needed as well. In real-world video applications, it is difficult to accomplish linear performance gains merely by increasing the number of general-purpose CPUs. You quickly reach the point of diminishing returns and have to use application-optimized processors to achieve highest system performance. Thus neither the economics nor the absolute-reliability requirements of video distribution support the use of general-purpose PC processors.

FPGAs have recently become more suitable in video applications because of their immense parallel processing capability and programmability. The highest-capacity FPGAs feature a large number of logic gates, and several vendors have implemented HD video encoders using anywhere from one to four high-density FPGAs, along with a few DSPs. FPGAs have the advantage of board density, but their power dissipation is high. Software upgrades using simple "C" programs aren't an option. Instead, any algorithm changes to the FPGA require time and effort because of the complex task of resynthesizing/reassigning gates, which can affect the logic timing and functionality of the solution.

Another possible solution is a dedicated HD AVC codec ASIC or SoC. The solution typically consists of a combination of hard-wired functions and an embedded processor, which creates an encoding solution that is rigidly defined in terms of how it handles the AVC algorithms. Any changes or improvements to the algorithm require a turn of silicon that is expensive (a 90nm mask sets costs close to $1 million), as well as taking anywhere from six to nine months (or more) to implement and deploy. Overall, the SOC approach lacks the flexibility and software programmability required for encoding applications in which the compression algorithm continues to evolve in time for improved video quality and lower bit rate.

A better way to handle AVC video compression algorithms is with high-performance digital signal processing (DSP) chips. But since the amount of real-time HD data to be processed is very large, several (20+) general-purpose DSPs are required. In addition, these devices are not designed for the high-bandwidth data sharing required for video compression. As a result, these solutions typically also require a number of FPGAs to communicate between video slices and achieve high-quality compressed video. Such a combination of DSPs and FPGAs produces a good picture, but the implementation is expensive to develop and maintain, and occupies a lot of space.

New HD H.264 encoder uses Telairity-1 processor
When developing its new NV2020-HD H.264 encoder, NVISION maintained its standard practice of using best-in-class solutions/technology. For highly optimized video processing, NVISION turned to Telairity for its Telairity-1video processor, which is unique to the broadcast market in that it delivers high quality HD video at a low bit rate, with low latency, and it's fully software programmable.

Telairity developed its Telairity-1 processor concurrently with AVClairity H.264/AVC codec software, with the goal of ensuring that hardware and software would work together optimally and seamlessly, as well as be adaptable for future upgrades to the H.264 standard.

Figure 1: For its new HD H.264 encoder, NVISION uses Telairity's programmable, multicore video processor for optimized, real-time HD H.264 video processing.

The centerpiece of Telairity's AVC compression hardware is the programmable multi-core Telairity-1 video processor, which combines five vector DSP cores on a single chip to maximize real-time performance and keep off-chip communications to a minimum. This integration minimizes board space relative to using a combination of general-purpose DSPs and powerful FPGAs, and translates into a more compact, cost-effective encoding system.

The Telairity-1 video processor has high bandwidth I/O, enabling effective sharing/exchange of video data, and eliminating video artifacts caused when HD video is processed in multiple slices. The high bandwidth I/O significantly reduces the need for high-speed/ high-density FPGAs, allowing the system design to be accomplished in a cost effective manner. Telairity-1 video processors are fully programmable, making it easy to implement standards extensions and algorithmic improvements in quality. Moreover, the Telairity instruction set is flexible enough to handle a variety of video compression standards and applications, making it the ideal solution for a multi-format HD encoder.

Figure 2: The Telairity-1 video processor has high bandwidth I/O for an effective exchange of video data, eliminating video artifacts caused when HD video is processed in multiple slices.

H.264 HD encoding: Now and in the future
The biggest market opportunity for HD H.264 encoders is satellite broadcast distribution. Satellite operators can double the number of SD channels as they switch from MPEG2 to H.264, or add new HD programming and video-on-demand channels, all of which are revenue-generating opportunities. HD H.264 encoders will also be used in distribution platforms for cable, terrestrial (TV networks and local stations), and IPTV broadcasting over bandwidth-constrained DSL lines. Market research firms have been forecasting enormous growth in IPTV households worldwide, and H.264 encoding will be an important catalyst for that growth because of the availability of excellent HD video at 6-12Mbps. There is also a need for HD H.264 encoders in sports broadcasting, and the NV2020-HD is designed have low latency (H.264 is still a young standard, and it will undergo many improvements and refinements as it matures. A number of Fidelity Range Extensions (FRexts) for H.264 have already been announced and higher native data types are likely part of its future. Most encoders can add significant value by inventing/fine-tuning algorithms that provide better results in their markets. Programmable products are the most future-proof, and give program providers a clear upgrade path as the H.264 standard evolves.

About the authors
Paul Greene
is the product manager of H.264 technologies at NVISION. With 20+ years working in video technology, Paul began his career as a chief engineer for video systems and moved on to become a video tape editor for 13 years. He holds a BA in Communications from Fairleigh Dickinson University.

Shubha Tuljapurkar is the VP of sales and marketing at Telairity. Shubha has 25+ years experience marketing ASICs, PC chipsets for system logic, graphics and multimedia, and various specialty memories and microprocessors. She has an MSc in Physics from The Indian Institute of Technology, Bombay and an MBA from Boston University. The authors can be reached at AggieFrizzell@NVision.tv.




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