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ST reports 65nm multistandard HDD physical layer IP

Posted: 11 May 2007 ?? ?Print Version ?Bookmark and Share

Keywords:Physical layer IP? macro-cell? ASICs? MIPHY? SoC?

STMicroelectronics has revealed what it says is the industry's first successful fabrication of the next-generation 65nm serial-interface MIPHY (Multi Interface PHY) physical interface IP.

The company designed the macro-cell to be integrated with other functions into low power SoCs supporting both 3Gbps and 6Gbps serial ATA (SATA) HDDs for mobile and desktop computing applications.

By implementing and verifying the 65nm interface design now, ST is preparing for the migration of SoC products to 65nm technology later this year, sharing with customers the benefit of lower power requirements and smaller physical size.

The proven IP will minimize the time-to-market for new products and reduce the development costs of new ASICs. In addition, the multiple standard capabilities (SATA Gen1, Gen2 and Gen3) of the new macro-cell will enable faster design validation for different markets and yield the benefit of larger-scale volume production while reducing costs for manufacturers by optimizing their engineering resources.

The fourth-generation MIPHY is a key IP block in ST's complete HDD IP portfolio. The device achieves a 35 percent reduction in die size and 30 percent reduction in power over the 90nm PHY. Further architectural improvements in equalization and transmitter and receiver circuitry have resulted in enhanced jitter tolerance and lower transmit jitter.

PHY macro-cells perform the high-speed serialization and deserialization of data to and from the drive and provide a 20bit-wide parallel interface to the link layer. In SATA applications, they can perform either host or device operations and can drive external signals directly without needing additional external components.

- Ismini Scouras

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