Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > EDA/IP
?
?
EDA/IP??

DDR2 IP and configurability

Posted: 14 May 2007 ?? ?Print Version ?Bookmark and Share

Keywords:PHY IC design? planning PHY step?

By Graham Allan
Mosaid Technologies

More and more SoCs are turning to off-chip memory resources, and frequently the chosen memory needs to be as economical as possible. That often leads to the utilization of DDR2 SDRAMs, which today represent the lowest-cost memory option. But DDR2 SDRAM brings along an awkward interface and command structure. Fortunately, there is a good semiconductor intellectual-property (IP) solution to the problem in the form of a combined memory controller and PHY.

In the past, interfaces to single- and double-data-rate SDRAMs were offered as soft-IP memory controllers. When mated to the hard I/O cells, they provided a complete solution for an interface to an off-chip DRAM. At the frequencies supported by DDR2 SDRAMs, however, a separate hard PHY has become a de facto requirement to support the memory controller logic.

A hard PHY is circuitry that has been designed in a full-custom mixed-signal environment. It targets the foundry and process technology the chip will use.

The process of creating a PHY for a specific design is unique to every chip. The planning process traditionally starts with the pad frame design, although designs for the package and even the PCB precede it. Once the pad frame is realized, the other PHY elements can be added to complete the PHY. While it may sound simple, the pad frame is driven by a number of items, including the exact interface configuration, type of package and number of power pins required.

This basic information needs to be assembled to start the planning process:

  • Determine the number of address pins, bank address pins, data pins, ranks and CK/CK_b output pairs required.

  • Identify reference clock source and type, package type, package model and bond pad configuration (such as wire bond vs. flip chip).

  • Determine the needed pad pitch.

  • List the clock frequency and test pin requirements.

  • Assemble the core power requirements for the ASIC and PHY logic.

In addition, the designer should find out if the design needs a CS_b pin (single-rank systems only), data mask pins and an error correction circuit.

The most critical issue to resolve is the I/O signal-to-power ratio. This represents the number of DDR data pin slots a single VDDQ/VSSQ pair can support. Numerous effects are taken into account in this analysis, including simultaneously switching output noise, IR drop, electromigration limits and electrostatic discharge requirements. The final signal-to-power ratio depends on the maximum operating frequency, package type, expected package RCL parasitics and external memory subsystem.

Once the pad frame is completed in a linear fashion, it may be too large to fit along one edge of the die. In such cases, or for other floor-planning reasons, a flexible PHY implementation must be completed to allow the PHY to go around the corners of the die.

The ultimate configurability comes with the breadth of an IP offering. Look for IP vendors that offer both controller IP and PHY IP, since the components have been designed and verified to work together. If you prefer to design your own memory controller, look for IP vendors willing to license the PHY separately.

About the author
Graham Allan
is director of marketing for semiconductor IP at Mosaid Technologies. He represents Mosaid on the Jedec Random Access Memory Standards Committee. Graham may be reached at allan@mosaid.com.




Article Comments - DDR2 IP and configurability
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top