Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

Survey: Taiwan IC design aims for high-end CE

Posted: 16 May 2007 ?? ?Print Version ?Bookmark and Share

Keywords:chip design? CE applications? Taiwan chipmakers? wafer foundry services?

The "2007 Taiwan IC Design House Survey" revealed a maturing chip design industry that's ready to take on more complex challenges to carve a name for itself in this highly competitive business.

Conducted in February and March 2007 by EE Times-Taiwan, the survey turned in responses from 58 design houses and covered the areas of process technology and design capabilities, major product applications, and design and manufacturing challenges.

While Taiwan chipmakers are traditionally known to be computer IC specialists, this year's survey showed a strong trend toward designing for high-end CE applications. More respondents said that they were developing chips with higher gate counts, a requirement in meeting the complex demands of feature-rich devices. Likewise, there was an apparent shift to smaller process technologies, an indication of the growing interest in downsized end-products. On the other hand, cost and reduction of design cycle time still emerged among the top challenges faced by design houses.

Workforce, service offerings
Thirteen of the 58 respondents had a workforce of more than 500, 34 had more than 100 and 16 had 50-100 personnel. On the number of IC design engineers, one respondent had more than 500, 19 had 100-500, nine had 50-100 and 30 had less than 50.

Twenty respondents said that aside from IC design, they also provided full system design services. Eighteen were also IP providers, 10 were also into testing services and nine said they also did wafer fabrication.

Of the 58 surveyed, 54 were contracting wafer foundry services. There were 52 that worked with Taiwan foundries, 10 that sent jobs to foundries in mainland China, while others also employed foundries in Singapore, the United States and Japan. The respondents identified cost as the top major difficulty they face in contracting wafer foundries, with 38 companies listing this as a priority concern. Other challenges were inadequate production capacity with 20 responses, cycle times with 18 responses and incompatible process technology with 15 responses. Compared to the previous survey, incompatible process technology got more responses this year.

On product offerings, 36 of the 58 design companies surveyed were engaged in ASIC design, 31 were into SoC design, 21 did standard ICs, 12 offered MCMs and SIPs, eight provided ASSPs and 12 were into PLD/FPGA-based designs.

On ASIC gate count, two respondents said they were designing chips with 5 million to 10 million gates, and five said they were doing designs with over 10 million gates. Notably, none of the respondents in last year's survey said they were designing chips with gate counts over 5 million. On FPGA designs, 11 respondents this year said they were developing devices with over 1 million gates, up from six respondents last year.

On process technology, nine respondents said they were doing designs at 0.13?m and 19 said they were using 0.18?m. Four respondents said they were designing at 90nm and below process nodes. In last year's survey, five companies were at 0.13?m and 22 were at 0.18?m. One respondent each affirmed using 90nm for analog designs and mixed-signal designs this year. Eight respondents said they did analog design at 0.13?m and 15 said they used 0.18?m, up from one and 14 respondents, respectively, from the last survey. In mixed-signal designs, nine respondents said they used 0.13?m and 17 said they were at 0.18?m, from two and 19 respondents, respectively, in the previous year. These figures reflect the steady adoption of smaller process technologies in the past year.

'Other consumer electronics'
On IC applications, 31 of the 58 respondents said they were making chips for "other consumer electronics," making this category the top choice this year, up from No. 4 last year. Coming in second was last year's No. 1, desktop and notebook PCs, which was picked by 22 respondents. Cellphones and digital cameras followed at No. 3 with 22 responses. The fourth spot this year was shared by WLAN/WLAN devices and DVD players, each getting 20 responses. At No. 5 with 19 responses were portable media players and toys/games.

The most popular digital chip type under development this year was SoCs with 23 responses, followed by digital ASICs with 19 responses. These two had traded ranks from last year. Holding the No. 3 spot was MCU/embedded MCU with 10 responses. Among analog chips, driver/controller ICs and analog ASICs topped the list with 16 responses each. Not far behind was analog/mixed-signal ICs with 15. Embedded MCUs with analog/mixed-signal functions came in at No.3 with 13 responses.

Cost and reduction of design cycle time still came out as the biggest challenges faced by engineers, each getting 33 responses. A far second was last year's No. 5, IP verification, with 12 responses, followed by IP availability with 10 responses.

- Joy Teng
EE Times-Taiwan

Article Comments - Survey: Taiwan IC design aims for hi...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top