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Multicore spurs RTOS, tool revisions

Posted: 16 May 2007 ?? ?Print Version ?Bookmark and Share

Keywords:multicore programming? debugging? C-language? RTOS?

Increased support for multicore programming and debugging is a theme that emerged at the Embedded Systems Conference Silicon Valley last April, as RTOS and tool providers improve model-driven design, virtual prototyping and C-language compilation.

QNX Software Systems has what it calls the first secure memory and CPU partitioning capability for multicore processors. Partitioning is often used in security-critical applications, because it guarantees resources for CPU time and memory, and ensures that a problem or attack in one partition won't affect the rest of the application. But partitioning today is limited to single processors, said Kerry Johnson, product manager at QNX.

"Translating partition information to multicore is challenging, because you need to replicate partition information across a number of processors," Johnson said. "Moving all this to multicore is a new thing that allows you to flexibly map partitions onto a multicore architecture."

With QNX's multicore partitioning technology, users of the company's Neutrino RTOS can have two partitions work on one processor, Johnson said. Alternatively, a partition can use multiple processors. The technology works for symmetric-multicore systems with homogeneous architectures.

Johnson said the partitioning can handle up to eight identical cores and can go as high as 32 for some architectures. It currently supports ARM, MIPS, PowerPC and x86 processors. The capability can make use of QNX's existing "bound multiprocessing" option, in which specific threads or applications can be bound to a specific set of CPU cores. QNX's Momentics suite provides visualization tools to aid in optimizing and debugging multicore designs.

Wind River Systems is broadening the multicore support in its Workbench On-Chip Debugging Edition. The product includes a networked, JTAG-based in-circuit emulator that supports multicore and multiprocessing applications.

"We can connect up to 128 processors on a single scan chain, and we can debug up to eight of those cores simultaneously," said Sandy Orlando, VP of on-chip debugging at Wind River. "It can be asymmetric or symmetric multiprocessing." The user can have a single debug environment for multiple cores.

With the new 2.6.1 release, this capability is extended to a number of new processors, including several from the Broadcom SiByte family, the Intel Xscale IOP 342, the Freescale MPC8641D 2.0 and the PA Semi PA6T-1682M. Additionally, the release lets users debug the Linux kernel, user applications and shared libraries without requiring kernel instrumentation, and it provides new Eclipse plug-in "view" facilities.

QNX supports multicore OS partitioning. Neutrino RTOS extends across multiple CPUs.

The ARM Realview development environment supports both single-core and multicore applications, and ARM announced a number of enhancements with its new 3.1 version at ESC. Among them is first support for the new Cortex-M1 processor, an ARM product designed for FPGA implementation.

Realview 3.1 also offers enhanced support for the ARM CoreSight debug-and-trace technology, allowing multiple trace streams and reduced pin count for debug and trace; a vectorizing compiler add-on for the ARM Neon SIMD architecture; and a new microlibC library for MCU applications. The version boasts intrinsic support for ARM DSP instruction-set extensions; performance improvements and tuning for ARM processor support; and enhanced Eclipse project management.

New compiler technology from Australian company Hi-Tech Software could one day aid multicore designs, but is currently aimed at single processors, particularly MCUs. Omniscient Code Generation (OCG) claims to generate object code for all program modules simultaneously, offering true global optimization.

"Rather than take a module-by-module or function-by-function view of the program when it's being compiled, OCG looks up the whole program," said Clyde Stubbs, Hi-Tech CEO. For smaller chips with multiple address spaces, OCG can help automate data placement. For larger chips with multiple register sets, it can perform programwide analysis and optimization of register allocation.

OCG looks at all code modules and collects data on register, stack, pointer, object and variable declarations. It uses that information to ensure consistent variable and object declarations between modules, optimize stack and register allocation, and delete unused variables and functions.

Stubbs said the technology can generate code that's 20 percent more compact than what Hi-Tech's existing compilers can achieve and up to 50 percent more compact than competing compilers' code. "The programmer can write what looks like standard ANSI C code without any special extensions to deal with the underlying architecture."

OCG serves the Microchip PIC18 MCU family and Cypress mixed-signal controllers. Hi-Tech plans to add support for all other Microchip MCUs and DSPs, as well as ARM7-based MCUs and 8051 MCUs.

Virtutech Inc., a provider of virtual-prototyping systems for software development, rolled out Simics VMP, a module in the Simics development suite that lets code run natively by leveraging hardware virtualization capabilities found in Intel and AMD processors. On-chip virtualization, traditionally used to let multiple OS run on the same server, is being applied to software development for the first time, said Paul McLellan, Virtutech's VP of marketing.

Virtutech will also field Simics 3.2, packing new features that let users incorporate virtualized software development into existing processes. The version improves integration with third-party debug and adds support for symbol tables.

Model-driven development
One way to facilitate creation of complex software is model-driven development using the Unified Modeling Language or Systems Modeling Language (SysML). Telelogic AB has introduced improvements to its Rhapsody line aimed at model-driven development. Rhapsody 7.1 is more tightly aligned with SysML 1.0 and offers greater support for agile development processes. A new Rhapsody for Telecom package includes those features of the tool set that are best suited for telecom. The Telelogic SDL Suite 6.0 offers improved kernel architecture for systems based on the Specification and Description Language.

Mentor Graphics Corp. promises to ease development of user interfaces with a new API for its Inflexion Platform UI for the Nucleus RTOS. The API lets the interface be changed without modifying the embedded device firmware, said Neil Henderson, general manager of the embedded systems division.

S2 Technologies Inc. has upgraded Stride, a tool set used for embedded software testing and verification early in the development process. Stride 2.1 adds support for controlling and automating C/C++ test code on the target, a wizard to generate test scripts automatically, and an enhanced user interface.

Finally, Aonix introduced an all-Java code solution using its Perc Ultra and Perc Pico tool sets runs faster than an equivalent Java program using C code for compute-intensive algorithms.

- Richard Goering
EE Times

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