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Chipmakers urge lower ESD target levels

Posted: 16 May 2007 ?? ?Print Version ?Bookmark and Share

Keywords:Electrostatic discharge? ESD target levels? ESD protection?

The Industry Council on ESD Target Levels is pushing to cut down on-chip ESD stress target levels by more than half. The proposal is expected to be hammered out in a white paper at this week's International Electrostatic Discharge Workshop in California, U.S.A.

The reduction is supposed to lower cycle times and costs for chipmakers struggling to meet the current ESD levels in new designs. According to the council, those levels are outdated, causing unnecessary debugging time, IC respins and product delays. The group maintains that its proposal will not compromise quality or performance.

The council, which hopes to muster industry consensus around its plan by 2008, will present the white paper to the Jedec standards body. Jedec is not expected to recognize the proposal as a formal standard but may endorse or "classify" the new ESD target levels.

As both chips and systems become smaller and more complex, product failures increase in tandem with the levels of electrostatic discharge. The cost for ESD-damaged devices ranges from a few cents for a simple diode to several hundred dollars for complex hybrids, according to the Electrostatic Discharge Association (ESDA).

Besides devising new target levels, the Industry Council on ESD Target Levels is also attempting to gain acceptance for the proposed ESD levels among the group members' customers. The council, which was formed last year, consists of 16 major companies: Analog Devices, Advanced Micro Devices, Freescale, Fujitsu, IBM, Infineon, Intel, LSI, Matsushita, NXP, Oki, Renesas, Samsung, Sarnoff, Texas Instruments and TSMC.

'Overkill' levels
Charvaka Duvvury, a fellow in TI's Silicon Technology Group and one of the industry's foremost experts on ESD, claimed that current target levels for ESD are "overkill" for today's IC designs. He insisted that the lower on-chip ESD target levels the council is proposing would not affect chip quality, reliability or performance. In extensive field tests conducted by the council, digital chips with reduced ESD levels had relatively few problems or field returns, he said.

The only challenge now is convincing the customers. "Naturally, there will be a pushback," Duvvury said. "One of the concerns among customers is that we're doing this for our own benefit."

But "it would not be in the chipmakers' best interests to lower the ESD levels unless it was safe to do so," market research house Forward Concepts Co. president Will Strauss noted. "I would side with the people that make the chips."

George Dudnikov, senior VP and chief technology officer for Sanmina-SCI Corp.'s PC-board and backplane divisions, said it is too early to tell if the proposed ESD target levels will have an overall impact on IC quality. However, he warned that "if yields begin to suffer, there might be a rebellion in the industry."

Sanmina-SCI is taking matters into its own hands. The contract electronics manufacturer has partnered with Shocking Technologies Inc. to devise a board-level embedded ESD solution. The technology essentially shifts ESD protection from the chip to the board, Dudnikov said.

For years, OEMs have implemented ESD protection on three fronts: the system, the board and within the chip itself. On the system side, OEMs tend to use standalone ESD devices, designed to protect a sudden static surge within a specific I/O, connector or other component. ESD devices adhere to the IEC 6100-4-2 immunity requirements, which call for a 15,000V air discharge level and a 8,000V direct-contact specification.

"For systems houses, the quality of the manufacturer is at stake. So ESD is becoming more and more important," said Tom Dugan, marketing director at Semtech Corp., a supplier of ESD protection devices and other products.

On the device side of the equation, all chip designs must integrate specialized diodes or other on-chip discrete circuitry for ESD protection. Many chipmakers have their own, internal ESD solutions, but Freescale, Sarnoff and a few others sell or license their respective technologies.

The Industry Council on ESD Target Levels!an ad hoc group that is not associated with ESDA!has already proposed changes to two main device-level stress-testing standards for ESD: the Human Body Model (HBM) and the Machine Model (MM).

Proposed levels
For more than two decades, chipmakers have developed digital IC products with on-chip ESD protection circuitry that supports the 2,000V level for the HBM and the 200V level for the MM. Under the new proposal, the council is pushing the industry to lower the HBM level to 1,000V and the MM target to 30V.

The supplier-customer cost of ESD protection is compared between two human body model specifications.

The HBM test simulates the electronic transfer of a charge from a human to a device. The MM test simulates the transfer of a charge from a machine to a device. There is no proposed change for the third primary ESD target level, dubbed the Charged Device Model (CDM). The CDM, which simulates a charge from one device to another, remains at 500V.

Technically, the CDM, HBM or MM specifications are not recognized by the standards bodies. For years, chipmakers and their customers have accepted these ESD specifications as a standard on an ad hoc basis.

But at the 90nm node and beyond, the current device-level ESD targets are too high, said council chairman and Infineon Technologies AG senior principal for ESD design Harald Gossner. Electrostatic device specifications must be lowered in order to reduce unnecessary time spent debugging, which is "delaying the time-to-market for ICs," he warned.

Today's stringent device-level ESD targets were originally devised some two decades ago, when factory floors lacked suitable ESD protection, and thus are outdated, Gossner said. And as digital ICs migrate down to the submicron realm, it's a struggle for chipmakers to meet those standards, he said.

Among the problems is a shift toward scaling ultrathin gate oxides in chip designs. According to a paper from TI, that trend "is causing a serious concern for both thermal damage as well as latent damage from the transients of the ESD pulse even with the presence of a clamp."

The problem is even more complex for SoC products, especially RF-enabled Bluetooth devices with digital capabilities. The industry has long accepted lower ESD protection levels for RF and compound semiconductors. "Much lower ESD performances are accepted in compound semiconductor devices (i.e., 250V HBM in many GaAs ICs) because no one to date has come up with technically or economically feasible on-chip protection solutions," a paper from Sarnoff noted.

Sarnoff, however, insists that it has an IP solution for ESD protection at 90nm and below. The company has licensed its so-called TakeCharge ESD solution to Epson, Renesas, Toshiba and others in Japan. In that country, ESD protection is a "selling point," said Sarnoff's Koen Verhaege. "The technical literature indicates that common ESD solutions are no longer technically and/or economically viable once you're designing below 90nm, but solutions do exist," he said.

Different approach
Freescale Semiconductor Inc. is taking a different and somewhat contradictory approach. On the one hand, it licenses its proprietary ESD protection technology to outside companies. On the other hand, it is also endorsing the lower ESD standards that the industry council is proposing. Jim Miller, design manager for ESD products at Freescale, said his company is attempting to gain a consensus for lower ESD standards in the industry as well as within Freescale itself. "The idea is to get the QA folks onboard," he said. "We are trying to lobby the goals within our own company."

On the systems front, Semtech has expanded its family of standalone low-capacitance protection devices. Its RailClamp line provides system designers with ESD protection for high-speed applications!without the high clamping voltage and high capacitance of competing solutions. The two devices, RClamp 1502B and RClamp 2402B, are designed with an ultralow capacitance of 0.6pF to protect high-speed data lines without signal attenuation, Semtech's Dugan said.

In a novel approach, Sanmina-SCI is using Shocking Technologies' specialty polymers for embedding ESD protection into PCBs. The companies are developing voltage-switchable dielectric materials!specialty polymers that instantaneously change from insulators to conductors when a preprogrammed bidirectional voltage is applied. "The technology is like an airbag in a car," Shocking Technologies president and CEO Lex Kosowsky said.

On another front, ESD testing and analysis expert White Mountain Labs has formed a partnership with SRF Technologies Inc., which supports semiconductor companies in I/O and ESD design.

- Mark LaPedus
EE Times




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