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Tool speeds up firmware debugging

Posted: 18 May 2007 ?? ?Print Version ?Bookmark and Share

Keywords:firmware debugging tool? Carbon VSP environment? OnDemand technology models?

Striving to meet the demands of firmware developers, Carbon Design Systems announced a new technology called "OnDemand" that speeds the performance of Carbon's Virtual System Prototype (VSP) environment for debugging. OnDemand models can automatically disable themselves when they're inactive.

The Carbon VSP environment compiles Verilog, VHDL and mixed-language RTL designs into a fast, cycle-accurate virtual prototype. VSP abstracts RTL into an optimized cycle-level representation, claiming to dramatically improve performance over RTL simulators. "Carbonized" models can also be imported into SystemC or C/C++ simulation environments.

Carbon models compiled with OnDemand don't actually run faster, noted Bill Neifert, Carbon CTO and founder. But the virtual prototype runs faster because the models disable themselves automatically when a transaction is complete. This lets software developers debug problems at instruction set simulation (ISS) speeds and only execute the hardware behavior when needed, Carbon claims.

"OnDemand is just the most recent optimization as Carbon targets itself more squarely at the firmware developer," Neifert said. "The firmware developer doesn't care about fast RTL models. He cares about a fast, pre-silicon platform that lets him debug, hopefully using the same tools he'll be using once he has real silicon."

Carbon's first optimization for firmware designers, Neifert said, was Carbon Replay. Introduced last year, Replay only executes the real RTL the first time the software is run, and then every subsequent run plays back the saved response from the first run instead of resimulating hardware.

In order to implement OnDemand, a small amount of monitor logic is included. This logic tracks the status of all state elements and input pins in the design. When these elements stop toggling, or start toggling in a cyclical matter, the monitor disables the model. It can be automatically re-enabled if any clock input changes value, or clock inputs change pattern from a currently recognized relationship.

"The monitor logic is small, but it does have an impact," Neifert said. "If your design block is going to be active more than 80 percent of the time, it is advisable to disable OnDemand execution, which can be done at run time."

Separately, Carbon announced that it has joined the MIPS Alliance Program, and has integrated its models with MIPS Technologies' MIPSsim instruction-set simulator and software debugger.

OnDemand will be shipped as a standard part of VSP and will be available later this year. It will be demonstrated at the June Design Automation Conference.

- Richard Goering
EE Times




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