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MIPS rollout spotlights high-end IP core

Posted: 30 May 2007 ?? ?Print Version ?Bookmark and Share

Keywords:32bit MCUs? high-end computing technologies? IP core?

MIPS Technologies Inc. has announced a new 32bit MCU that includes superscalar, out-of-order technology perfect for high-performance applications.

The MIPS32 74K line consists of two synthesizable, 1.04GHz cores, dubbed the 74Kc and 74Kf. The 74Kc is a base integer core while the 74Kf combines the integer core and a high-performance floating point unit.

Based on a 65nm process technology from Taiwan Semiconductor Manufacturing Co. Ltd, the 74K is built around a superscalar, 17-stage pipeline architecturewith enhanced DSP instructions.

Unlike its previous 32bit, RISC-based embedded cores, MIPS' 74K product makes use of a number of technologies normally found in high-end computing: out-of-order dispatch, asymmetric dual-issue, branch prediction and a 128-bit L1 cache interface. The 74K is a single-threaded core, but future products may include multi-threaded technology.

Despite the use of such technologies, the 74K is by no means considered overkill for new and future embedded applications, said Pete Del Vecchio, product marketing manager for MIPS. ''For low-end processing, it is really not appropriate,'' Del Vecchio said. ''But for certain applications, you need this level of performance.''

The 74K is designed for high-volume applications such as DTV, set-top boxes, DVD players/recorders, broadband access systems, residential gateways and other systems, he said.

The new family also supports advanced branch prediction, thanks to three 256-entry branch history tables and an eight-entry return prediction stack. It also features enhanced DSP instructions, which are 60 percent faster than the 24KE cores from MIPS. It also supports L2 cache and extensive clock gating for low-power applications.

- Mark LaPedus
EE Times

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