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New Quartus II suite speeds up compile times

Posted: 30 May 2007 ?? ?Print Version ?Bookmark and Share

Keywords:Quartus II software? IP cores? FPGA design tool?

Altera Corp. claims that its Quartus II software version 7.1 can enable designers to achieve more than two times faster compile times and half the memory footprint of the nearest high-end FPGA. Customers can also begin designing today for the entire Arria GX FPGA family in both the subscription edition and Web edition of Quartus II software.

System features
Altera's compile time improvement address the productivity needs of customers relying on Quartus II software to design their next-generation systems. Using advanced place-and-route algorithms, Quartus II software version 7.1 and Stratix III FPGAs deliver, on average, more than 2x faster compile times compared to competing high-end 65nm FPGAs. To further accelerate the design cycle, customers using multiprocessor computers see an additional 20 percent reduction in compile times over single-processor computers. Altera's Quartus II software is the only software from an FPGA vendor offering multiprocessor (such as the Intel Core 2 Duo and Quad and AMD Athlon 64 X2) support.

The new version also includes several productivity updates to Altera's SOPC Builder automated system development tool. An improved infrastructure and a more responsive GUI allows for faster implementation of large systems and a new Avalon Streaming interface is optimized to send streaming data between two IP blocks. Version 7.1 also includes a new Avalon Memory-Mapped clock-crossing bridge, a pipeline bridge and a scatter-gather direct memory access (DMA) controller for improved system performance.

Customers can use Quartus II software version 7.1 to design for all members of Altera's recently announced product families, including Arria GX, Stratix III and Cyclone III FPGAs. With immediate support for the new Arria GX family in both the subscription edition and web edition of Quartus II software, designers have opportunities to get their PCIe x1 and x4, GbE and Serial RapidIO designs to market quickly.

Key enhancements
Version 7.1 of Quartus II software includes a number of features and enhancements to help customers achieve the highest productivity and performance when designing with Altera FPGAs, CPLDs and structured ASICs. The enhancements are as follows:

?Faster TimeQuest timing analyzer - improves productivity with faster timing closure featuring improved compile time, less memory usage and easier conversion from Altera's classic timing analyzer
?New compile-time advisor - recommends compile-time saving settings during the design flow to improve productivity
?New in-system sources and probes editor - reduces verification time by allowing designers to drive stimuli to the device and sample internal nodes during run time
?Expanded synthesis - provides faster design entry with a new text editor, new HDL templates and true dual-port RAM inferencing
?Updated parallel flash loader - offers quicker device configuration with 2x faster flash programming times and burst mode support for flash devices
?Enhanced usability - simplifies the design process and accelerates the sign-off process by using the advanced Quartus II message console
?Smart notification - automatic notifications via the Quartus II desktop of new software downloads and service packs.

Both the subscription edition and free web edition of Quartus II software version 7.1 are now available for download. The subscription edition is also available in DVD format by request, said Altera. Subscribers will receive Quartus II software, the ModelSim-Altera edition and a full license to the IP Base Suite, which includes ten of Altera's most popular IP (DSP and memory) cores. Annual software subscription is $2,000 for a node-locked PC license. Quartus II design software supports major operating systems, including Microsoft Windows XP Professional x64, Microsoft Windows XP and 2000, Unix (Solaris 8 and 9), Red Hat Enterprise Linux 3.0 and 4.0 and SUSE Enterprise Linux 9.




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