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FPGA kits streamline DDR2 SDRAM devt

Posted: 31 May 2007 ?? ?Print Version ?Bookmark and Share

Keywords:Spartan-3A FPGA? Virtex-5 FPGA? 65nm?

Xilinx Inc. rolls its low cost Spartan-3A FPGA development kit for DDR2 SDRAM interfaces, the Virtex-5 FPGA development platform (ML-561) for multiple high-performance memory interfaces (I/Fs) and the memory interface generator (MIG) software version 1.7. These complete solutions enable FPGA users to quickly implement and verify custom memory interface designs across various data rates and bus widths thus, accelerating time-to-market.

According to Xilinx, the solutions, including device characterization, data capture circuitry and memory controller, are all fully verified in hardware using memory devices from industry leaders such as Micron Technology.

The Xilinx memory interface solutions are developed using production-qualified 90nm Spartan-3A and 65nm Virtex-5 FPGAs, supporting up to twice the bus-width of any other FPGA based solution shipping today. Low-cost memory interfaces can be built rapidly with the I/O optimized Spartan-3A FPGA family while Virtex-5 FPGAs with built-in 75ps calibration circuits, flexible I/Os to connect memory on any side of the FPGA and innovative packaging to minimize crosstalk for reliable operation of wide memory interfaces offer the highest bandwidth.

Low-cost tools
The Spartan-3A FPGA development kit allows designers to get a DDR2 SDRAM interface up and running right out-of-the box in less than an hour. The kit includes all components needed to complete a low-cost design, said Xilinx. It also includes the following:

?Spartan-3A starter kit board with Spartan-3A (XC3S700A-FG484) FPGA and 32Mx16 DDR2 SDRAM device
?Pre-verified reference designs show 267Mbps DDR2 SDRAM operation with lowest speed grade Spartan-3A FPGA (Spartan-3A FPGA family supports 333Mbps today with 400Mbps characterization pending)
?Demonstration files using Xilinx ChipScope Pro in-circuit logic analyzer, enabling users to verify data transfer and control signals
?Popular parallel and serial interfaces and connectors
?Evaluation disk containing ISEdesign software and the ChipScope Pro analyzer?USB FPGA download cable
?Quickstart guide in different languages.

The Virtex-5 FPGA based development platform (ML561) features multiple high-performance memory interfaces and hardware-verified reference designs with in-depth ChipScope Pro demonstration files to enable implementation and verification of the high bandwidth memory I/Fs. These include 667Mbps DDR2 SDRAM Registered DIMM with 144 bit I/F, 400Mbps DDR SDRAM, 300MHz QDR II SRAM 72bit I/F and 333MHz RLDRAM II 36bit I/F.

Memory interface generator
The Memory interface generator (MIG) is a free, user-friendly parameterizable software tool to create memory interface designs in unencrypted RTL for Xilinx FPGAs, DDR2/DDR SDRAM, QDR II SRAM, and RLDRAM II interfaces. MIG supports multiple memory architectures, device and package combinations that provide system designers with the flexibility to easily customize their own design. The MIG is integrated in the Xilinx CORE Generator software and provides RTL source and constraints files through a graphical interface for ultimate user flexibility. The designs are generated in a modular format to provide distinct physical layer, user interface and controller blocks providing users with simplified verification capabilities.

The Spartan-3A development kit for DDR2 SDRAM interface is immediately available for $235, while the Virtex-5 FPGA based ML-561 platform is available for $5,995. Free download of RTL source reference designs and the Memory Interface Generator (MIG) version 1.7 are immediately available at Xilinx's website.

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