Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > EDA/IP
?
?
EDA/IP??

IC designers favor less complex DFM

Posted: 01 Jun 2007 ?? ?Print Version ?Bookmark and Share

Keywords:less complex DFM tools? simple DFM approaches? foundry collaboration for DFM?

Current approaches to design-for-manufacturing (DFM) may be yielding too little for the amount of effort and cost involved. This is what IC design experts pointed out during the IEEE Electronic Design Process (EDP) workshop in April. Rather than throw complicated analysis tools at designers, speakers said, DFM is best addressed through design rules, preverified blocks and improved standard-cell libraries.

Sorin Dobre, staff engineer at Qualcomm Inc., said his company is using advanced DFM tools and is engaging in extensive collaboration with foundries. And yet, he said, the cost of DFM is doubling at each process node, while yield improvements are not keeping pace. "The question is, what is the value provided by DFM tools?" Dobre asked.

DFM tools and process design kits (PDKs) lag new silicon processes by six months or more, and process models are "very inaccurate," Dobre said. One thing that would work, he said, is building silicon intellectual property (IP) with less variability and with restricted design rules (RDRs).

DRC extension
Freescale Semiconductor is having success using DFM as an extension of design rule checking (DRC), said Rajesh Raina, DFM and design-for-test methodology manager at Freescale. Raina said the company has also done promising research into increasing standard cell size.

Keynoter Leon Stok, IBM Corp.'s EDA director, argued that throwing more DFM information at designers is not a viable approach. He called for a "prescriptive CAD" methodology that takes a designer's "prescription" for design characteristics and uses automated elaboration tools geared to a given process. For fast design, he said, DFM effects should not be exposed outside preverified blocks.

Anyone who expected Patrick Groeneveld, chief technologist at Magma Design Automation Inc., to argue on behalf of DFM analysis tools would have been surprised. "We have to keep all our DFM problems inside our standard cells," he said. "Simple rules get you more than throwing a very complicated tool at the end of the design process."

DFM defined
The "big" definition of DFM is the replacement of all current IC CAD tools, said Gary Smith, chief analyst at Gary Smith EDA. The "little" definition includes resolution enhancement technology (RET), design-for-yield (DFY) and the "true" DFM tools used by designers.

RET and DFY are used after silicon tape-outs and do not involve designers, Smith said. Thus far, he said, only Clear Shape Technologies Inc. has introduced a "true" DFM tool for design engineers, "and the big question is, will they use it?" If DFM follows the experience of DFT, Smith said, it will take seven years before it's commonly used in designs.

"Users badly need a workable DFM flow," Smith said. "Point tools are no longer adequate. This is driving a DFM consolidation, and unfortunately for the startups, it favors big EDA vendors."

At 90nm, Dobre said, Qualcomm started collaborating closely with foundries; used recommended design rules; and tapped lithography simulation, critical-area analysis (CAA), rule-based data preparation and IP silicon qualification. On a scale of 1 to 20, he said, the DFM cost was 2; the impact on yield, time-to-market and performance was 5.

At 65nm, Dobre said, Qualcomm developed a much closer relationship with its foundries, participated in process development and used DFM-oriented PDKs. The DFM cost doubled; the DFM impact was close to that for 90nm. "We spend a lot of time and resources integrating these solutions into our design flow, and then we get silicon and see some marginal improvements," he said.

Qualcomm is moving on to 45nm, where it is even tighter with its foundries and has much better modeling of chemical metal polishing effects. But the DFM cost has doubled again, Dobre said, because teams of engineers are needed to develop qualification processes, calibrate models and run new tools. When, he asked, will the benefits catch up to the costs?

Possible solutions
RDRs are one possible solution. Another needed change, Dobre said, is the earlier availability of easy-to-calibrate DFM process models, along with standardized test vehicles used for extraction and calibration. Qualcomm wants to see model-based DRC become a reality for physical signoff, lithography and CAA tools integrated into the design flow, and a consistent verification methodology based on silicon data.

Dobre said Qualcomm developed a "power-aware integrated design ecosystem" for 90nm designs and successfully used DFM optimization to reduce leakage current by 20 percent. "There are new technologies that might have a much bigger impact on parametric yield than just using DFM alone," he said.

Foundry collaboration and DFM tools enable 45nm DFM 'ecosystem.' (Click to view full image)

There's a business case for DFM, Raina said. Given a 90nm design with six layers, 26 masks, a wafer cost of $3,030 and a volume of 30,000 per month, a 1-percent yield increase translates into $1.5 million monthly.

Raina said Freescale has been able to improve yields by using DFM rules as an extension of design rules. "Whatever we're doing in libraries for DRC, we just provide some extra rules, in the same format, for DFM guidelines," he said. In the future, he said, Freescale wants to move to model-based DFM, but for now, the approach is entirely rules-based.

Magma would presumably like to sell DFM analysis tools, but Groeneveld!asserting he was speaking for himself!argued that putting signoff DFM tools into a physical synthesis loop is a "bad idea."

'Ballpark is enough'
Analysis is slow, highly accurate and fully automatic. Synthesis tools are fast and must use inaccurate analysis!"ballpark is enough," Groeneveld said. He said signoff abstraction levels are needed to avoid costly iterations, and that it's important to keep signoff levels alive.

"Cells are the place to hide your DFM issues," Groeneveld said. "The major work for most DFM companies is patching up bad standard-cell designs. If standard cells had been designed properly, those companies would never have had any business."

"I think simple things work," Groeneveld said. "We have to use as few contacts as possible and keep wires as short as possible. Complicated tools have no place here." He called for very simple "zero order wisdom" for synthesis tools: "Bigger cells are better. Lower density is better. Keep it regular and uniform."

IBM's Stok noted that many DFM efforts focus on feeding manufacturing information back to the designer. For those who care most!full-custom designers working in new processes!that information is too unreliable. And ASIC designers don't have time to deal with the DFM information, he said.

"Can we have a prescriptive CAD methodology that would provide a methodology and a set of rules to give the designer what he wants?" Stok asked. Then "we could get the CAD industry back to what it's good at: improving designer productivity."

- Richard Goering
EE Times




Article Comments - IC designers favor less complex DFM
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top