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IBM gets on the road to 3D packaging

Posted: 01 Jun 2007 ?? ?Print Version ?Bookmark and Share

Keywords:3D packaging? Big Blue? through-silicon vias?

News that IBM Corp. this year will sample its first commercial devices to make direct metal connections between chips marks a small but significant milestone on the road to 3D packaging. This emerging style of silicon design promises advances in performance, power and cost for a broad array of systems.

In 2008, Big Blue will sell production quantities of a power amplifier that sports as many as 100 direct metal links to a power ground plane. That could lower power consumption by as much as 40 percent for a device that is a key component in cellphones and Wi-Fi adapters.

IBM is one of as many as a dozen large and small companies pursuing so-called through-silicon vias or other forms of 3D packaging as the next big leap in direct chip-to-chip links.

Three-dimensional packaging goes a step beyond today's SoC and system-in-package approaches. Rather than use intermediary substrates and wires, raw silicon dice will slot into one another with tiny metal-filled holes a few dozen microns wide. The technique could open the way to linking very different kinds of devices with far less power and higher data rates than is possible today.

"You are hacking a couple of orders of magnitude off the wiring used in today's millimeter wire bonds to deliver these micron-size vias," said Sitaram Arkalgud, director of the interconnect division of Sematech, a chip industry R&D group. "The ultimate goal is to find a way to link CMOS, bio, MEMS and other devices in a heterogeneous stack. For this, the industry will probably need a standard 3D wiring protocol for placing the vias." Arkalgud will help draft the 3D chip road map.

Climbing 3D ladder
IBM will take a stepwise approach to shaking out the new technology. Beyond the power amplifier, it plans to use the technique to link a microprocessor to its ground plane to stabilize power distribution across the chip. That will require more than 100 vias to voltage regulators and other passives.

IBM has completed a prototype of such a design and estimates it could cut a CPU's power consumption by 20 percent. However, "the decision has not been made yet on where to insert this in our product plans," said Wilfried Haensch, a senior research manager in IBM's exploratory research group.

The endgame is to use thousands of the interconnects as a high-bandwidth link between CPUs and memories. IBM is already converting the custom Power processors used in its Blue Gene supercomputers to through-silicon via packaging. The new chips will mate directly with cache memory chips. A prototype SRAM using the technology is being fabricated in IBM's 300mm production line using 65nm process technology.

MicroPILR aims for smaller, denser interconnect. Approach requires new copper material and etching techniques.

The new technology could become a major factor in the ongoing battle between Intel Corp. and Advanced Micro Devices Inc. AMD co-develops process technology with IBM but might need to take out a special license to the IBM packaging technologysomething it might do at the 32nm generation, said David Lammers, director of the WeSRCH Website created by market watcher VLSI Research Inc.

Intel, for its part, is also exploring through-silicon vias. Intel plans to apply the technique to a future generation of its Terahertz research processor, said Justin Rattner, head of Intel's R&D group, at the Intel Developer Forum last year.

Through-silicon vias can shorten the distance that data on a chip needs to travel by 1,000 times, and allows for the addition of up to 100 times more interconnects per device, according to IBM. "This breakthrough is a result of more than a decade of research at IBM," said Lisa Su, VP of IBM's semiconductor research and development center.

Chipmakers have been working on 3D interconnects for years, but to date, the technology has been viewed as an expensive niche. Engineers have been researching through-hole vias as well as wafer-level bonding and other alternatives. The need for 3D interconnects and packages has become more critical amid what some call a looming interconnect crisis experts believe could emerge by 2009. The crisis stems from the fact that chip scaling is shrinking the aluminum or copper interconnects in chip designs, causing potential timing delays and unwanted copper resistance.

But even with the IBM announcement, the industry still faces "a huge number of headaches in cost, yield and test," said Brandon Prior, a senior consultant with Prismark Partners, a consulting firm specializing in packaging issues.

Young technology
The emerging die-stacking technology remains immature and expensive. Heat dissipation in the silicon stacks is another major problem. A few companies are sampling through-silicon via products, but none have shown the potential to replace today's entrenched wire-bonding techniques or new advances in package-on-package technology.

Indeed, approaches to stacking multiple package substrates remain the hottest growth area in packaging today, said Lee Smith, a business development manager with Amkor. The Jedec group has set standards for the approach, and the techniques are rapidly being applied for cellphone stacks that include both memory and logic chips, Smith said.

Some experts believe memories will be among the first devices to deploy through-silicon vias. But traditional wire-bonding and current chip-stacking techniques will continue to make strides and may nudge out the need for 3D packaging in many applications, depending on the cost of the various approaches.

Sematech has started work on a cost model it will use to map the different technologies to the applications for which they are most suited, said Arkalgud. An initial mapping should be available by the end of the year, but the document will evolve over time, he said.

Indeed, getting companies focused on a few approaches to 3D packaging and the challenges they create is one of the biggest hurdles today, said Arkalgud.

"The industry is at a point where there are many solutions but no consensus on the way forward. If you ask five people how to do this, you will probably get more than five answers," he said.

Once a consensus emerges, the industry needs to tackle an array of technical issues. They include how to bind and align 3D chip stacks as well as how to uniformly create and handle the ultrathin wafers they require. Simply drilling and filling the tiny viaswith aspect ratios of 10:1 and diameters as small as 90mwas IBM's chief challenge, said Haensch. He declined to divulge details of the company's process.

Once engineers solve the manufacturing problems, the technique will open up new possibilities in chip design. If processors can sport a direct, high-bandwidth link to multiple SRAMs, they may not need an internal cache. Such caches consume the brunt of the die area in a CPU.

- Rick Merritt and Mark LaPedus
EE Times




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