Performing SE design with digital audio amps

One of the biggest advantages of digital amplifiers is the flexibility of the digital data path for design reuse. Because the signal is kept in the digital domain until it is practically at the speakers, there is much more flexibility in signal routing. This flexibility also applies to processing both on-the-fly and on the production line with stuffing options and/or firmware changes. A single-ended (SE) operation is a common mode where the digital amp is used. This article discusses the basics of SE design and the engineering trade-offs involved.

The digital amplifier typically has a two-stage architecture, a pulse-width modulation (PWM) processor followed by the power stage. The logic-level PWM processor accepts the audio data, usually in IIS format. It performs audio processing and converts the pulse-code modulated data into PWM data. Typically, the PWM processor is controlled through I?C to change volume, tone controls or other audio processing functions like equalization. Most PWM processors have another key feature, which is the ability to change signal routing even "on-the-fly." This allows the designer flexibility in PCB routing or the ability for the user to route content to different speakers. The power stage takes the 3.3V PWM signal, translates it to a higher voltage, and applies it to the speaker through the MOSFET H-bridge and second-order LC filter.

The power stage contains a MOSFET H-bridge. This is where MOSFETs are used as switches to apply the +V voltage across the speaker, either in a positive or negative direction. Bridge-tied load (BTL) is the normal configuration for most stereo power stages where the speaker is connected between two MOSFET half-bridges. SE refers to when each speaker is driven by a single MOSFET half-bridge. The channel count is doubled in SE mode, compared with BTL mode. But the power per channel is cut to about 25 percent for a given output load. In SE mode, the +V voltage is applied to the speaker in a positive direction when the PWM signal is high. When the PWM signal is low, the speaker is connected to ground.

The digital amplifier typically has a two-stage architecture, a pulse-width modulation processor followed by the power stage.

Design trade-offs
SE operation for a digital amplifier is not much different from an SE operation for a linear audio amp. The main difference is that the reconstruction filter (second-order LC filter) sorts out the higher frequency components from the PWM signal, leaving the baseband audio signal. Applying the audio signal directly across the speaker results in a large DC voltage across the speaker, which is equal to PVDD/2. Because the speaker impedance has a predominant inductive component, this is equivalent to placing a large DC voltage across an inductor and causes the current to increase linearly to a very large value, possibly damaging the speaker.

A large capacitor (DC-blocking cap) is placed between the amplifier and the speaker to filter out this DC component. However, this cap also attenuates the lower audio frequencies and has a 3dB point of approximately 1/(2 R_spC), where R_sp is the impedance of the speaker. To pass more frequency bandwidth through the speaker, a larger capacitance can be used. However, this comes with cost and PCB-area trade-offs.

In the SE configuration, the audio signal is referenced to ground. In other words, one speaker terminal is connected to ground. Another way to achieve DC blocking is to use a split-cap configuration where the audio signal is now referenced to PVDD/2. From an AC perspective, there is no difference between an SE digital amp with DC-blocking cap configuration and an SE digital amp with split-cap configuration, as long as Csm = Cb/2. In addition to the capacitance being cut in, half the current rating of Cs can be half of Cb, and the ESR can be twice that of Cb with no change in audio or thermal performance.

The biggest advantage of the split-mode configuration over a blocking cap is that the power supply rejection ratio (PSRR) is increased. The figure is a PSRR measurement of the TAS5086/5142 evaluation module (EVM) from Texas Instruments. The TAS5142 power stage is configured as SE in this EVM. Some might be surprised that an open-loop, SE amplifier can have this much PSRR. This is because voltage changes in PVDD (ΔPVDD) will also be at the midpoint of the split-cap (ΔPVDD/2). So across the speaker, changes in PVDD are cancelled out.

The SE split-mode configuration requires that two other design issues be addressed. As previously mentioned, the audio signal after the reconstruction filter has a DC value of PVDD/2. If the capacitors Cs are ideal, both will charge up to PVDD/2 and there will be no DC component across the speaker. Since both capacitors are not ideal and will have a tolerance, however, the DC voltage will not be equal to PVDD/2. Thus, the speaker will have a DC voltage across it when the audio signal is first applied to the speaker, resulting in a pop when powered up. Another related issue occurs because the split-caps take a finite time to charge with a time constant of RC. As long as the MOSFETs do not begin switching until the split-caps are charged, this is not a problem. In practice, this is difficult to do, and large pop noises can occur.

The solution to these issues can be a power stage with a half-bridge specifically dedicated to quickly charging this voltage to PVDD/2, which is available with the TAS5186A. With a 50 percent duty cycle, the DC voltage output is PVDD/2 and the split-caps are quickly and accurately charged. Another way to charge the split-caps quickly is to use an op amp. Using an op amp is a proven method for split-cap charging when a dedicated half-bridge is not available. In practice, SE amplifier audio performance data—including power-on pops, SNR, PSRR and total harmonic distortion plus noise—are quite good with only a small degradation in audio performance from that of BTL.

- Kevin Belnap
Marketing Manager, High-Performance Analog Home Audio Group
Texas Instruments Inc.