Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

Rivals play down threat of Mentor's Sierra acquisition

Posted: 14 Jun 2007 ?? ?Print Version ?Bookmark and Share

Keywords:Sierra acquisition? EDA rivals? IC implementation?

Mentor Graphics Corp. may be hoping to reshape the IC implementation market with its acquisition of Sierra Design Automation, but the three vendors who dominate that market today don't think it will happen. Synopsys, Cadence Design Systems and Magma Design Automation all seem to regard Mentor's Sierra acquisition as a minimal threat, and their own positions in 65/45nm IC design as strong.

Mentor's acquisition of Sierra brings together Sierra's Olympus-SoC netlist-to-GDSII implementation suite with Mentor's Calibre design rule checking (DRC) and design for manufacturability (DFM) tools. While newcomer Sierra holds a distant number four market position in IC implementation today, Mentor believes there's a "discontinuity" in 65/45nm design that only Sierra's variability-aware IC placement and routing tools can fill.

A validation
Not so fast, said Saleem Haider, senior director for product marketing at Synopsys' implementation group. "Synopsys has already recognized that variation is going to be a dominant effect as designs move down to 45nm, and we have been executing on it for a number of years," he said. "We view Mentor's acquisition as a strong validation that we have the right strategy."

"A complete solution requires variation-aware signoff, which is a key component [Sierra is] still missing for addressing parametric yield," Haider said. "Sierra's routing technology is relatively new, and prior experience has shown that this is something that takes a very long time to mature. Given that Mentor is getting a late start and 65nm and 45nm designs are well underway already, Mentor has a long road ahead of them to gain meaningful customer traction."

Haider claimed at Synopsys' IC Compiler already offers concurrent multicorner/multimode optimization, a key claim behind Sierra's Olympus-SoC. "In addition, IC Compiler has the industry's best routing technology that is a result of many years of R&D investment, which is an area where Sierra is just getting started," Haider said.

More work ahead
Eric Filseth, VP of Encounter and DFM marketing at Cadence Design Systems, said that Sierra's toolset has so far been used as "a fast multicorner optimizer, a specialty tool which was plugged into their customers' main flows after routing but before metal fill. They have a lot of work ahead to make it competitive as a real implementation system," he said. "And there's always the possibility that statistical timing methods might simply eliminate multicorner anyway."

"This move seems less about getting into implementation than about trying to shore up Mentor's problem in verification," said John Lee, general manager for the physical verification business unit at Magma Design Automation. "What's really driving this is customers' desire for incremental verification and the resulting need for Mentor to defend Calibre. Leaving aside the two big question marks surrounding this transactionthat Sierra's technology has seen limited penetration, and that the price and terms of the transaction invoke a non-trivial level of risk for Mentorwe think they're already too late to the party."

Lee said that Magma is meeting customer requirements with its Quartz DRC/LVS/DFM "in the loop" capabilities and incremental verification within Magma's Talus platform. Magma updated Quartz DRC and LVS prior to the Design Automation Conference.

Analyst's view
Gary Smith, chief analyst at Gary Smith EDA, said the EDA industry is around two-and-a-half years behind 65/45nm requirements in most categories. While Magma, Sierra and DFM startup Pyxis meet 65/45nm ASIC layout requirements, he said, neither Synopsys nor Cadence has a fully capable 65/45nm layout tool. The two requirements are parallel processing and rule-based DFM routing.

"It's been interesting that during the past few years there has been an attitude shift at Mentor," Smith said. "In the past they seemed to accept the position of number three. A few years back they started seeing themselves as the next number 1. They aren't there yet but they sure have a running start."

- Richard Goering
EE Times

Article Comments - Rivals play down threat of Mentor's ...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top