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Toshiba develops tech for next-gen NAND flash

Posted: 14 Jun 2007 ?? ?Print Version ?Bookmark and Share

Keywords:NAND flash memory? cell array? cell density?

Toshiba Corp. has developed a technology that can meet the future demand for higher density NAND flash memory.

The new technology involves a three-dimensional memory cell array structure that enhances cell density and data capacity without relying on advances in process technology, and with minimal increase in the chip die size. In the new structure, pillars of stacked memory elements pass vertically through multi-stacked layers of electrode material and utilize shared peripheral circuits.

The company's new approach is based on innovations in the stacking process. Existing memory stacking technologies simply stack two-dimensional memory array on top of another, repeating the same set of processes. While this achieves increased memory cell density, it makes the manufacturing process longer and more complex. The new array allows increase in memory cell density and while making it is easier to fabricate. In addition the technology offers less increase chip area as peripheral circuits are shared by several silicon pillars.

The etching technology drives a through-hole down through a stacked substrate, like multi-layer sandwich of gate electrodes and insulator films. Pillars of silicon, lightly doped with impurities, are deposited to fill in the holes. The gate electrode wraps around the silicon pillar at even intervals and a pre-formed nitride film for data-retention, set in each joint, functions as a NAND cell.

The NAND flash memory functions through batch processing of cells, in large numbers of elements connected in series. The new array increases density without increasing chip dimension, as the number of connected elements increases in direct proportion to stack height.

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