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Single-chip Serdes rolls for 2.5Gbps GPON apps

Posted: 15 Jun 2007 ?? ?Print Version ?Bookmark and Share

Keywords:passive optical network? Serdes? FPGA?

Micrel Inc. launched the SY87725L, a single-chip programmable Serdes that supports multiple passive optical network (PON) standards and rates including asymmetric gigabit passive optical network (GPON) with data rates up to 2.5Gbps on the receive side and 1.25Gbps on the transmit side.

This product offers complete clock recovery and data retiming circuitry, along with an integrated 4bit serial-to-parallel data converter, on the receive side. On the transmit side, it also includes a synthesizer with an integrated 4bit parallel-to-serial data converter. The device is targeted at BPON, GPON, GEPON and EPON applications in the growing fiber-to-the-home and fiber-to-the-premises markets.

"The SY87725L Serdes manages all the high frequency signals in an optical network unit (ONU) and is an ideal low-cost solution for a programmable or upgradeable ONU when pairing with a low cost FPGA," said Thomas Wong, VP of high bandwidth products, Micrel. "With the flexibility of the transceiver and the low cost [capability] of an FPGA, our customers can provide ONU solutions only limited by their imaginations."

SY87725L has a 4bit interface and a DDR option is included to reduce the clock frequency. This allows the use of the lowest cost FPGA without increasing the I/O pins. The device also features a novel auto-align circuit that further simplifies the critical timing requirement. The part operates on a single 3.3V supply and offers 1W typical power consumption. The parallel 4bit I/O interfaces feature LVDS I/O. It is available in lead-free (10-by-10mm) 64-pin and EPAD-TQFP package options.

SY87725 is currently available in volume and is priced at $9.95 for 1,000-piece quantities. An evaluation board is also available, said Micrel.

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