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Industry tackles approach to DFM, DFY issues

Posted: 18 Jun 2007 ?? ?Print Version ?Bookmark and Share

Keywords:DFM DFY at 65nm? DFM DFY issues approaches? Design Automation and Test in Europe?

As design-for-manufacturing (DFM) and design-for-yield (DFY) take on critical importance at the 65nm node, discussions proceed apace about how best to handle them. At the last Design Automation and Test in Europe conference, experts from chip, EDA and foundry companies used a medical metaphor to frame the debate, asking whether it's better to be "surgeons" who deal with DFM and DFY issues at tape-out, or "family doctors" who, with an eye toward prevention, minister to the design starting at the register transfer level.

The consensus: Prevention is always advisable, but surgery may be unavoidable at technology's bleeding edge.

Numerous preventive approaches can be applied when using and developing intellectual property (IP), said ARM Ltd fellow Rob Aitken. For lithography issues, options depend on the type of IP. A key issue is maximizing DFM compliance without unduly increasing die area. For some classes, such as I/O and analog IP, all foundry DFM recommendations can be followed. For soft IP, recommendations for use of physical IP and DFM-friendly reference flows can be provided.

A challenge for the family-doctor approach, Aitken said, is a lack of data: When IP is being developed, mass production in a process node has not begun, so subtle effects are often unknown. Careful design practices can anticipate some issues and avoid them, but the process cannot be perfect.

Downside to surgery
Similarly, a challenge for the surgical approach is a lack of patient history. "Just as the appropriate treatment of a torn ligament will change depending on whether or not one intends to participate in an upcoming triathlon, the appropriate treatment for design issues changes depending on the criticality of the circuit, the yield and performance targets of the design and other critical factors," Aitken said.

Antun Domic, senior VP and general manager of the implementation group at Synopsys Inc., observed that "at 65nm, design and manufacturing can no longer be handled separately." Physical synthesis has been extended to encompass DFM/DFY, slashing the number of iterations and respins that would otherwise be needed to correct the thousands of problems detected at GDSII (the tape-out specification that links the design process with manufacturing).

As the industry has advanced from 90- to 65- to 45nm, said Carlo Guardiani, senior director of DFM at PDF Solutions Inc., yields for complex SoCs built with new technologies are increasingly dictated by systematic and variability effects that are probabilistic functions of the actual circuit layout properties.

Nanometer DFM provides a complex design scenario. All the right ingredients need to be there for manufacturing/yield.

Every process technology, Guardiani said, is characterized by a unique set of yield sensitivities that is determined by the choice of process integration, lithography equipment and resolution-enhancement technology recipes and equipment calibration. Unless those process sensitivities are accurately quantified and their impact on product yield properly modeled, he said, it is impossible to predict that a particular design choice will always be yield-savvy.

Jean-Pierre Schoellkopf, director for advanced design at STMicroelectronics, said that until the 0.13?m node, "if you could manufacture each structure, you could manufacture the entire chipwhat you designed on the polygon layout tool was what you got on the wafer." Engineers had simple design rules with yes/no, pass/fail criteria for the design rule checker. In "the rare case of an emergency," Schoellkopf said, the surgeons ruled the day.

Today, at 65nm and beyond, features are manufactured with 193nm lithography, causing an order-of-magnitude increase in the number of defects and faults. One result is that at 65nm, the cost of test per transistor is only 200 times lower than the cost of manufacturing, vs. the 1,600x differential seen at 130nm, said Schoellkopf.

Clinical history
"Designers and process engineers need to collaborate in analyzing the variables that contribute to critical design specifications," he said. "This means that manufacturability must start at the chip design level. The family doctors, with their deep knowledge of the patient's clinical history, can play a fundamental role."

Schoellkopf warned, however, that it is not enough to include DFM specifications in physical design and verification tools, since that method does not address how various components will react to each other when integrated into an SoC. That requires looking across hierarchical boundaries to see how the data in one cell interacts with data outside the cell, since it might be possible to improve the manufacturability of one layer by manipulating another.

This more-comprehensive model requires a new infrastructure that supports a feedback loop between designer and manufacturer. The feedback loop should include means of modeling the manufacturing constraints, verifying IC layouts and translating manufacturing-related issues for the designer.

Patient's well-being
Douglas Pattullo, technical director for TSMC Europe BV, maintained that the core issue is not the skill set of a "surgeon" or a "family doctor," but rather who knows the "patient" best and is most focused on that customer's well-being.

Perhaps not surprisingly, Pattullo claimed that foundries are in the best position to determine the patient's condition. "In this analogy, the foundries work like a central medical-records departments for the associated hospitals, clinics, teaching establishments and research groups," he said. The foundries may have produced test chips two years or more before the fabless vendor submits its first design, and they have already seen the success and failure of different implementations.

Joe Sawicki, VP and general manager of the design-to-silicon division of Mentor Graphics Corp., concurred with the need to find flexible approaches.

"In the end, each approach has an important role to play," said Sawicki. The design must be delivered downstream meeting the vast majority of manufacturing requirements. Then the DFM tool needs to have sophisticated, flexible analysis and improvement algorithms in place to handle the lastand thereby the most difficultproblems.

- Nicolas Mokhoff
EE Times

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