Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

Power analysis tool aims at 45nm, 65nm designs

Posted: 18 Jun 2007 ?? ?Print Version ?Bookmark and Share

Keywords:power integrity analysis? power analysis tool? RedHawk-ALP tool? power gating memories?

Extending its IC power-analysis capability to include several emerging methodologies, Apache Design Solutions Inc. has introduced RedHawk-ALP which provides dynamic power integrity analysis for power-gated memories, variable-threshold CMOS (VTCMOS) circuits with substrate back-biasing and on-chip low-dropout (LDO) voltage regulators. The company will aim the new offering at high-end designs in 65nm and 45nm processes, said Dian Yang, VP of product management at Apache.

With RedHawk-ALP, Yang said, "we're really talking about ultralow power. That means mobile applications where standby power is less than 5 percent of the total power, such as cellphones and PDAs. Those designs can use traditional power-gating techniques, but they get to the point where more is needed."

One new technique is multithreshold CMOS or power gating for memories, so that designers can shut off memory blocks to save power.

"It sounds simple, but in terms of circuit technology it's extremely difficult," Yang said. "When you turn off a large regular structure, it can cause a tremendous amount of noise for neighboring blocks, and you will likely destroy all other operating logic at the moment."

RedHawk-ALP runs an analysis of the "rush current" that's generated when memories are switched off. The rest of the chip is still operating when the rush current takes place, and the analysis is part of a full-chip, circuit-level simulation. According to Yang, the accuracy of the rush current analysis is to within 5-10 percent of silicon.

A second technique is VTCMOS with substrate back-biasing, which reduces leakage current by dynamically altering the substrate voltage. This introduces noise on the supply source and increases variability in the circuit's behavior.

A third technique involves the use of on-chip LDOs to deliver desired voltages to different parts of the chip. LDOs are traditionally separate chips, and now designers are embedding them inside SoCs, Yang noted. "The problem is that the LDO is a very difficult analog circuit," he said. RedHawk-ALP runs a full transient circuit simulation including the LDO, so that users can see the waveform of the LDO's output.

Yang said that Apache hasn't run any silicon measurements yet to test the accuracy of RedHawk-ALP's LDO analysis, but he thinks it will be within 10-20 percent of silicon, or closer.

RedHawk-ALP will be available for production shipments in the third quarter, and lists for $330,000.

- Richard Goering
EE Times

Article Comments - Power analysis tool aims at 45nm, 65...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top