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The intricate dance of cutting power consumption

Posted: 18 Jun 2007 ?? ?Print Version ?Bookmark and Share

Keywords:cut power consumption in consumer electronics? UPF for low power? power management techniques?

The Consumer Electronics Show 2007 in Las Vegas have taught us that there are three things that really count in the electronics design communitylow power, low power and low power. Consequently, SoC designers must simultaneously provide more functionality and longer battery life for handheld devices. This is a huge challenge.

To date, designers have had to choreograph a complex dance on their own, bringing together specialized design techniques, low-power tuned intellectual property (IP) blocks and libraries, and semiconductor processes. Some teams have stumbled; some leading-edge design teams have performed the dance well.

To help the broader design community, however, the EDA community must provide designers with automated solutions that smooth the path. Those solutions must optimize power while addressing all of the other design and market requirements, including speed, cost and IC-manufacturing yield.

The greatest opportunities to reduce power and energy consumption in a consumer device come through trade-offs and decisions made at the system level. Decisions about system partitioning, in which functionality is implemented in hardware vs. software, and about component and IP selection have the greatest impact on power reduction, system performance and functionality.

For example, a critical architectural feature for managing power in a HDD-based MP3 player is a software-controlled data-buffering system that allows the HDD to deliver several minutes' worth of music at a time, then to spin down until more music is needed. While many current cellphones are highly optimized at an architectural level for voice communication, consumer pressure is forcing architects to add other features (i.e. e-mail, streaming video, MP3 players). In turn, this forces system architects to use increasingly aggressive architectures to manage power. To support that effort, the EDA community continues to improve its tools for modeling power at the system level, providing feedback to system designers about the impact of their architectural decisions.

Hardware techniques
Once the system architecture is determined and the main application ICs are specified, many hardware power management techniques can be applied.

RTL designers can take advantage of a broad set of minimally invasive techniques (i.e. clock gating, logic- and cell-level power optimization) and multithreshold voltage-based design as part of a standard synthesis-based design flow. The automatic application of these techniques can reduce power while maintaining performance, testability and manufacturability. The only additional requirements are a library with integrated clock-gating and logic cells offering multiple drive strengths and multiple threshold levels, and the tools to use those library features. EDA tools today provide such capabilities, and use of the techniques is becoming routine.

More aggressive power management methods are still on the leading edge of design practice and EDA tool capability.

Dynamic power is proportional to V2. So to minimize dynamic power, the key is to reduce the supply voltage. Designers are starting to use multiple voltage regions on-chip: higher voltage regions for high-performance blocks like processors and cache, and lower voltage regions for other blocks that operate at lower frequencies. This approach requires level shifters to be inserted between blocks operating at different voltages. The most aggressive designs dynamically scale the supply voltage and clock frequency to key components, such as a processor, depending on their workload. This technique is referred to as dynamic voltage and frequency scaling (DVFS).

Leakage problem
As geometries continue to shrink to 90nm, 65nm and beyond, leakage current is becoming a major problem, limiting battery life in handheld devices. To minimize leakage power, design teams are starting to use power gatingshutting down power to blocks that are not being usedusually by turning power off using on-chip switches. This requires isolation cells between the regions that are powered off and those that are powered on, and a strategy for retaining state during power-down.

These techniques are extremely effective for consumer applications with peak processing needs (e.g. video encoding/decoding) but spend a substantial portion of time in less-demanding modes of operation. Using an adaptive approach to power management, one can design the chip for maximum performance but enable far lower-power operation when the demands on select blocks within the design drop off.

With the right hardware design and other considerations, both DVFS and power gating can be controlled through software, offering significant energy savings and prolonged battery life.

Both of these adaptive techniques require considerably smarter design automation techniques and more intelligent IP. Designers need a means of specifying power intent, namely, which regions are powered by which supply, which regions can be powered down and when, and the strategy to be used to retain state during power-down. They typically want to specify this design intent independently of the RTL, since a given RTL block may have different power intent in different applications.

So implementation tools need to place the power intent and insert level shifters, isolation cells and retention registers in the appropriate places, and route power to all the devices in the chip correctly. In particular, the tools need to buffer signals appropriatelythat is, with buffers that are powered on when the signal is needed and powered down when it is not. Some of these routing rules can become quite complex.

With the golden RTL, UPF is used systematically throughout the design process to reduce both static and dynamic power consumption.

Sign-off tools must now include voltage-dependent timing and power-grid integrity. Formal and dynamic verification must deal with the changes in design behavior that result from the addition of power gating. IP suppliers must also help with a wider range of low-power IP, including a range of level shifters, isolation cells, retention flip-flops and power gating switches. To support DVFS, the library must also be characterized for use over various voltages, not just at one or two specific operating points.

Aligning tools
Key players in the industry are collaborating to deliver low-power solutions that bring more automated EDA tools, smarter IP, standard formats and more power-stingy processes together into true end-to-end solutions. EDA and IP companies have worked within the Accellera standards organization to develop Unified Power Format (UPF). UPF provides a mechanism for describing the power intent for a design independently from the RTL. It allows the designer to define power domains, isolation strategies and retention strategies for power gating. It also allows designers to define a level-shifter strategy and a power state table for dealing with multiple power regions. UPF aligns all the tools throughout the design flow to implement and verify against the same set of power reduction strategies.

Used with the golden RTL for a design, UPF is used systematically throughout the design process to reduce dynamic and static power through DVFS and power gating.

-Mike Keating
Fellow, Advanced Technology Group
Synopsys Inc.




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