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Rethinking DFT strategies in nanometer designs

Posted: 18 Jun 2007 ?? ?Print Version ?Bookmark and Share

Keywords:at-speed testing? DFT strategy? DFM rules analysis? Embedded Deterministic Test? compressed pattern diagnosis?

One of the challenges confronting the semiconductor industry is the need for more-advanced manufacturing tests. At-speed test has become standard at the 130nm process node. As the industry races to the 90nm and 65nm nodes, manufacturers are exploring other types of advanced test.

Chee-Chun Tay, applications consultant at Mentor Graphics Corp., tackles more of DFT strategies in nanometer designs.

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