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Graphics SoC targets small TFT LCDs in cars

Posted: 19 Jun 2007 ?? ?Print Version ?Bookmark and Share

Keywords:TFT LCD panels? display controllers? automotive graphics?

Toshiba America Electronic Components Inc. (TAEC) has expaned its family of automotive graphics and display controllers with a new SoC targeted at instrument-cluster applications ranging from back-up camera displays to full-size, reconfigurable instrument clusters.

Designated TX4964FG, the new single-chip solution drives and manages the small TFT LCD panels increasingly found in instrument clusters in medium- to high-end automobiles. The highly integrated device integrates the CPU, hardware-graphics engine, TFT LCD panel controller, digital-camera interface and frame-buffer memory in a compact 176-pin QFP package with 0.5mm pin pitch. Its 4Mbytes of embedded DRAM eliminate the need for external RAM ICs, thus reducing system-level power and contributing to the small footprint.

TX4964FG replaces four ICs and reduces design complexity through the integration of a powerful processor, an advanced graphics display controller with dedicated accelerator functions and a comprehensive range of on-board peripherals and interfaces. The SoC features Toshiba's low-power, high-performance MIPS-based TX49/L4 64-bit CPU core operating at 120MHz. An integrated graphics display controller together with specialized accelerator engines deliver graphics processing and display-control capabilities. Dedicated hardware engines for cluster graphics can deliver up to 32bit RGBA colors. The graphic accelerator enhances the display output and offers high-quality anti-aliasing to ensure smooth graphics display. The frame grabber works with a wide variety of input data formats; it captures and processes video images and supports applications such as rear-view monitoring.

The TX4964FG also includes a built-in 64bit Toshiba TX49/L4 core, a 64bit MIPS I, II, III ISA-compatible processor core with additional instructions. The core operates at 120MHz maximum operating frequency and integrates 8Kbytes instruction cache and 8Kbytes data cache.

The SoC features a unified memory architecture with a high-performance quad-bus structure with separate busses for the CPU, video, graphics and graphics-acceleration functions. The device's graphics display controller with 8-bit alpha blending on all operations enable very high quality displays. Meanwhile, the graphics accelerator engines provides hardware acceleration for flexible transformation operations and for rotation and scaling operations.

Other product highlights include a frame grabber for video capture and several peripheral controllers, including a three-channel external bus controller, a four-channel DMA controller, interrupt controller, serial I/O consisting of a two-channel UART and a two-channel enhanced serial interface and a two-channel CAN-bus controller.

The chip features 1.2V core-supply voltage, 2.5V and 3.3V I/O supply voltage and low-power dissipation estimated at 1W. It operates in the automotive/industrial temperature range of -40C to 85C ambient temperature. The chip was manufactured in 90nm process node.

Product samples will be available in the third quarter with volume production scheduled to begin in 2008. The device is priced at $25 each in 10,000-piece quantities.

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