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Digital front-end tool rolls for TD-SCDMA

Posted: 22 Jun 2007 ?? ?Print Version ?Bookmark and Share

Keywords:TD-SCDMA? digital front-end? digital radio applications? DSP?

Xilinx Inc. and Multiple Access Communications (MAC) Ltd partner to deliver a TD-SCDMA digital front-end (DFE) reference design solution based on the Xilinx system generator for DSP tool.

The reference design solution reduces the development time required for the complex digital algorithms found in TD-SCDMA DFE radio applications. Consisting of example reference designs, full-speed working demo and complete IP library that include optimized system generator IP blocks for digital up conversion (DUC) and digital down conversion (DDC) functions, the TD-SCDMA DFE reference design solution enables users to construct 3GPP-compliant DFE designs for various base station configurations.

The TD-SCDMA DFE reference design solution enables developers to reduce design risk and provides a quick time-to-market route from concept-to-production for digital radio applications. The IP library encapsulates the signal processing functions that determine compliance with the 3GPP requirements in such a way that complexity of these functions is hidden from the library user. With this approach, developers can save many months of algorithm development and many years of hardware development time given the multiple antenna and carrier configurations, ranging for single carrier-single antenna to 6 carriers-8 antennas per sector.

Hao-Fei Chen, general secretary of China's TD-SCDMA Forum, said, "After reviewing the Xilinx TD-SCDMA DFE reference design solution, we are convinced that it can help China companies to shorten their time to market in delivering TD-SCDMA standard compliant wireless base stations of various configurations, from single- to multi-carrier designs."

The TD-SCDMA DFE reference design solution is enabled by Xilinx high-performance Virtex-4 platform FPGAs, which offer superior performance and cost-effective DSP processing capability, enabling a lower cost-per-channel than competing solutions. Moreover, Virtex platform FPGAs allow in-field upgrades, which make the base station more adaptable to evolving technologies and standards.

The TD-SCDMA DFE reference design supports up to six carriers per antenna and offers a flexible intermediate frequency input or output. DUC performance highlights are an EVM of 1.6 percent RMS and ACLR >80dB, for an occupied bandwidth of >99.9 percent. The DDC block provides ACS >75dB, blocking >80dB and a low latency signal path delay of just 14.9?s.

The free Xilinx TD-SCDMA DFE reference design is now available for qualified customers at Xilinx's

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