Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > EDA/IP
?
?
EDA/IP??

Intel drafts inverse litho to cover EUV delay

Posted: 25 Jun 2007 ?? ?Print Version ?Bookmark and Share

Keywords:EUV lithography? EUV delay? inverse litho?

With the possible delay of its extreme ultraviolet (EUV) lithography, Intel Corp. disclosed it is developing a design-for-manufacturing (DFM) technology that could extend optical scanners to the 22nm node.

The company is now working on "computational lithography," which is a form of so-called inverse lithography. Inverse lithography, along with EUV and double patterning, are among the lithography options that Intel is evaluating for the 22nm node (32nm half-pitch) for logic. Inverse lithography is said to replace optical proximity correction (OPC), one of the most computationally intensive portions of the IC DFM flow.

EUV replacement
Unlike OPC, inverse lithography uses an outcome-based technology to determine the mask features that produce the desired on-wafer results. The technology is said to solve many of the challenges in the deep sub-wavelength era!thereby extending optical lithography beyond 45nm. The technology could push out the need for EUV, which is already late to the party due to technical problems. Intel, for one, is banking on EUV for the development of chips at the 22nm node for logic in the 2011 time frame.

But the ongoing lack of power sources, resists and condenser technologies for EUV is causing a growing concern in the market. Two companies!ASML Holding NV and Nikon Corp.!are delivering or will shortly deliver EUV tools, but those systems are still in the early prototype stages. Nikon is expected to ship a prototype EUV tool to Intel by year's end.

A production-worthy EUV tool is not expected to be shipped until the later stages of the 22nm node. Some doubt that EUV is even viable. Besides the technical hurdles, an EUV tool is expected to cost between $70 million to $100 million!if or when a real production tool is shipped.

Intel insists that it is still interested in inserting EUV at the 22nm node, but the chip giant acknowledged that the technology still has some issues.

"EUV is progressing," said Mike Mayberry, director of components research and VP of technology within Intel's manufacturing group. "EUV is technically challenging, but we're not done yet."

Other options
But based on Intel's roadmap, the chip giant is hedging its bets!if EUV is late again or fails to appear. Like the 65nm node, the company will use "dry" 193nm lithography for the critical layers at 45nm. Intel's main lithography vendor for logic is Nikon.

At 32nm, Intel plans to move to 193nm immersion lithography. Then, at 22nm, the company is exploring a range of options, including 193nm immersion with double patterning, EUV and inverse or computational lithography.

No decision has been made!yet. But Intel's Mayberry discounted nanoimprint lithography, saying this technology is not an option.

Meanwhile, Intel disclosed its efforts in computational lithography. Originally, this technology was supposed to be targeted for 32nm, but Intel is confident that it can insert 193nm immersion at the node, thereby bypassing inverse lithography.

- Mark LaPedus
EE Times




Article Comments - Intel drafts inverse litho to cover ...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top