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Designing in the age of 3D systems

Posted: 25 Jun 2007 ?? ?Print Version ?Bookmark and Share

Keywords:3D stacking? 3D multipackage solutions? 3D EDA tools?

By Charles White, Tessera Inc.
David Seeger, IBM Research

This is just the beginning of the 3D revolution.

Market research firm Prismark Partners estimates that more than 1.4 billion 3D packages were produced in 2005. Over time, however, current 3D components!predominantly die-stacked and package-stacked devices!will be displaced by direct silicon integration and new generations of very fine-pitch 3D multipackage solutions.

A combination of silicon carrier and 3D chip technologies provide an interconnect density that supports 40,000 or more wired interconnects per cm?, allowing approximately 1TBps of bandwidth between chips. This represents an interchip bandwidth that is higher than what is available in most packages today.

These technologies use 20?m solder microjoints on 50?m pitch, compared with conventional packages with 100?m solder balls on 200?m pitch. Copper wiring on top of the silicon substrate has minimum feature sizes of 1?m wires on 2?m pitch, compared with conventional packages that can only support a 20?m minimum line width on 40?m pitch. In the future, full 3D integration will enable another order of magnitude of interchip bandwidth.

Emerging design approaches
Integration in a chip stack enables lower power drivers because of the excellent electrical performance of interconnects. An example of an annular copper-filled via showed a resistance of about 2mΩ, inductance under 1pH and capacitance of a few femtofarads. A 20?m microjoint had a resistance of about 30 mΩ. Hence, the I/O power that is required when single-ended buffer I/Os are used on a silicon carrier is less than a fraction of the power needed for the elastic drivers used in a conventional package.

System-in-package (SIP) and package-on-package (PoP) approaches have an existing high-volume manufacturing infrastructure and offer substantial cost advantages over relatively immature through-silicon via technology. New fine-pitch, low-profile technology, such as Tessera's microPILR, can achieve densities of eight layers in less than 1.2mm while allowing each individual layer to be fully tested and burned-in before stacking. Once these are designed, tested and productized, they are highly reusable, reducing time- and cost-to-market.

Ultimately, as the industry adopts chip-stacking technology, it will mature into a handful of cost-competitive solutions. For example, IBM recently announced that it will begin volume shipments of chips with through-via connections next year. Similarly, Samsung has introduced its stacked DRAM chip technology. Fabrication of these structures can be completed in a fully depreciated silicon fabrication facility with design rules that are several generations older than advanced fabricators. These older technologies still enable much higher bandwidth than conventional packages, since the minimum feature size is on the order of 1?m line widths on 2?m pitches. Meanwhile, conventional organic packages can only support 10?m lines on a 20?m pitch.

New native 3D IC architectures address cost head-on. For example, Tezzaro Semiconductor's 3D memory architecture has one or more memory arrays stacked on top of a memory controller. Unlike a monolithic approach, the memory array and control logic wafers each use smaller dice and processes optimized for their specific functions. Tezzaro estimates that its manufacturing cost will ultimately be about one-half the cost per bit of conventional memories.

Design methodologies
The optimal utilization of the third dimension requires a careful design of the overall 3D system architecture. Planar design involves placing each component in x,y space with a rotation. In 3D design, developers must determine the number of layers in a stack and place components in x,y,z with rotation and flip. Very strong spatial visualization and reasoning are essential prerequisites for successful 3D design.

Pass-through connections!a direct electrical connection between two or more pins of a component-are very common in 3D. They are used to supply power, ground and signals up a stack. Pass-through connections can be difficult to comprehend when identical components are stacked, yet they provide unique I/O at the same pin location.

Another useful 3D design technique is the use of components that can be mounted either face up or face down. One example of this approach is a PoP device that has identical pad footprints on the top and bottom, with each pad connected by pass-through vias. This allows two such components to be mounted on the opposite sides of an interposer so that their I/Os are shared, with only pass-through vias required on the interposer.

Discrete passives consume substantial real estate, particularly as levels of integration increase. Integrated decoupling in the package and on the die will be essential for high-performance designs. Substrate-integrated capacitors have been improving steadily and have reached 0.8nF/cm? with laboratory results in the range of 3?F/cm?. Passives integrated on silicon carriers have demonstrated capacitance of 2.5?F/cm? with straightforward extendibility to more than 10?F/cm?.

Four challenges
But designing with 3D packages does have its challenges. Heat, power integrity, design automation tools and testing all require special attention.

Heat degrades performance, reduces reliability and increases power consumption. Three-dimensional integration multiplies the number of transistors in a volume, which often, but not always, exacerbates the problem. By reducing package thickness and using large thermal vias, package substrate technologies such as Tessera's microPILR can reduce thermal resistance by as much as 50 percent. Direct liquid cooling can provide even greater cooling capability. In fact, cooling over 500W/cm? has been demonstrated.

Design architecture can also influence thermal performance. Consider, for example, a 32bit memory bus connected to four banks, where each bank requires four 8bit-wide memories. The memory devices can be stacked for breadth or stacked for depth. In the stacked-for-breadth case, each four-dice stack sources all 32bits for a bank. In the stacked-for-depth case, each four-dice stack contains an 8bit slice for each of the four banks. Stacking for breadth means that each stack independently sources all 32bits, resulting in four times the thermal load, but also four times the bandwidth of the stacked-for-depth design. In the stacked-for-depth case, power dissipation for each stack is the same as if there were only one chip. Stacking for depth is an example of the "magic" of 3D, where four times the capacity is achieved in the same footprint at the same power dissipation.

In terms of power integrity, 3D can mitigate some challenges while creating new ones. The shorter average interconnect length reduces parasitics. When a die's vertical height increases in distance from the decoupling capacitors, however, the inductance increases. Finer geometries afforded by silicon carriers and advanced substrates allow for more power and ground pins, reducing delivery inductance. Design architecture can multiply power integrity challenges, as in the stacking-for-breadth case.

But with proper design, engineers can mitigate signal integrity and crosstalk concerns. They can modify the signaling schemes to create effective shielding that minimizes crosstalk. Consider wiring on a silicon carrier, for example. Instead of placing all of the signal lines on the same wiring level, the engineer can split them to multiple levels. This still allows for very high bandwidth and sufficient shielding to minimize crosstalk.

Currently, 3D EDA tools are in their infancy. Tools that enable silicon co-design in the package are emerging, but right now, they are limited to relatively simple 3D configurations. One significant milestone in 3D design will be achieved when a major tool vendor supports a data model that can fully represent the complete spectrum of 3D configurations. Once that exists, the next challenge will be the implementation of seamless co-design and hierarchy management. For example, designers currently lack the ability to drag a die from inside one layer of the 3D stack to another. To handle a range of possibilities, 3D interconnect!including stacking architectures, implicit connections, multilayer interposers and pass-through vertical connections!will require complex floor-planning, placement and routing algorithms.

Debugging test is another substantial challenge in 3D design. The high interconnect density and buried interconnect dramatically limit signal observability. SoC designers confront this challenge in all of their designs. Fortunately, 3D gives engineers the opportunity to test and debug elements before assembly. The ability to integrate proven elements shortens the design verification time.

Composite yield refers to the probability that a higher-level assembly is free of defects. Historically, this has been one of the most significant roadblocks to 3D adoption. Package-in-package and PoP approaches hit the challenge head-on by allowing full test and burn-in. Advances in wafer-level at-speed test and full wafer-level burn-in will enable direct semiconductor integration. Ultimately, the use of redundancy, dynamic repair and real-time fault detection and isolation will enable low-cost, high-volume 3D systems.

New 3D solutions will enable the realization of computation capability per unit volume that will be two orders of magnitude greater than what is possible today. For example, this technology can be used to miniaturize a cell-based, blade-prototyping platform by a factor of 200, to yield a higher-performing, multidice 3D integrated module.

As 3D technology matures, completely new interconnect architectures will emerge. The level of integration will go up dramatically, ultimately achieving devices that contain more than a trillion transistors at today's package sizes.

About the authors
Charles E. White
is the VP of Advanced Technology Initiatives at Tessera Inc. He holds a bachelor's degree in electrical engineering from the University of Illinois and a master's degree in engineering management from Stanford University. He can be reached at cwhite@tessera.com.

David Seeger is the Senior Manager in Advanced Packaging at IBM Research. A member of the Senior Leadership Team at IBM's Packaging Research and Development Center, Seeger holds a PhD in organic chemistry from Yale University. He can be reached at seeger@us.ibm.com.




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