Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

Commentary: Hope emerges for analog layout automation

Posted: 25 Jun 2007 ?? ?Print Version ?Bookmark and Share

Keywords:analog physical design automation? design automation? parameterized cells? 65nm? 45nm?

By Jim Solomon

There's a gaping hole in analog layout design automation. Over the past few years, a number of EDA companies have tried to fill it, but largely failed due to overambitious plans or lack of appropriate infrastructure. But today, a unique combination of new technology and open infrastructure makes me believe that substantial progress can at last be made in automating analog physical design.

Twenty years ago when I was at SDA/Cadence, we delivered a layout editor that made use of parameterized cells or PCells. Since then, a mild form of schematic-driven layout has been added to most analog flows, but very little else has changed. When I talk to analog designers around the globe, I find that virtually all of them are still using that same old manual layout flow, passing a sized schematic to a layout designer, who uses a manual layout editor for physical design.

Compare this to the powerful technologies that digital SoC designers have at their disposal. They can start from RTL and go all the way to GDSII using a well-coordinated set of tools. Analog physical design has a long way to go in comparison.

But that's not all. Another problem with analog physical design is migration, or lack of it. While those modern digital flows enable easy migration between processes, analog must for the most part be manually reworked for each process node.

Many attempts at analog physical design automation have failed. Analog synthesis is a complete disappointment and other technologies have not gained much traction. The problem is that high-performance physical design is inherently very demanding, requiring the layout designer to deal with multiple hierarchical symmetries and possibly conflicting constraints. Earlier analog automation tools have not been able to manage this complexity in an effective enough way. As a result, the majority of analog designers have just not adopted these approaches.

What's needed is a fundamentally new, yet pragmatic approach, one that respects and augments the skills of both the layout and circuit designers. To be successful, an analog physical design automation tool has to work hand-in-hand with these experienced designers, integrating with the tools they now use.

Even more important, the resulting layout must closely resemble that which is created by the human hand. Analog designers have historically not been very interested in new approaches, but we are now finding them to be open to tools that make them more productive, as long as they fit into the way they do things today.

If analog physical design automation is going to succeed, it has to win the placement battle. Analog device placement is no trivial task. When working on a circuit block of 20 to 50 devices, an experienced designer may specify a dozen or more symmetries, alignments, matches and other constraints that need to be followed to get maximum performance and minimum area.

The designer applies these constraints not just to devices but also to groups of devices and hierarchies. He or she will also create constraints to enable the router to do its job, shielding some nets, keeping others short, making others matched or parallel. Many of these routing constraints must also be understood and honored by the placer.

A practical method for entering and handling these constraints is critical to making this new approach work. Constraints are independent of both device sizing and process technology. A transistor pair which must be matched at 65nm must also be matched at 45nm, even though the device sizes and design rules change.

It is these constraints that define the analog physical design automation solution and produce layout which can be migrated between process variations and nodes. An open standard for design constraints which can be accessed by any tool is a necessary part of the "open" story for OpenAccess.

To summarize the requirements, any new approach to analog physical design automation has to create efficient device placements from these user-provided constraints, it must do so in a matter of minutes and it must fit within existing user environments.

As challenging as this has seemed over the years, we are now beginning to see viable tools coming to market. The OpenAccess database effectively opens up current design flows to allow integration of new best-in-class software components.

Interoperable PCells are now available that work in any OpenAccess tool. EDA vendors are now collaborating on an open constraint specification. Startup companies are working on placement technologies which meet the requirements I've described. Early results look very promising, and there should be major progress demonstrated at this year's Design Automation Conference.

These pieces of the puzzle did not exist even one or two years ago, but they are becoming available now. In the more than 20 years since I started SDA/Cadence, I have never been more optimistic than I am today about the advances that can be made in filling the holes in analog physical design automation.

About the author
Jim Solomon
founded Solomon Design Automation in 1983, later renamed Cadence Design Systems. Today he serves on the boards of Ciranova, Silicon Navigator, Applied Wave Research, Pyxis Technologies, Nascentric, and Gemini Design Technology.

Article Comments - Commentary: Hope emerges for analog ...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top