MCUs offer high performance at lower power, cost

Atmel Corp.'s new customizable MCU delivers up to 8x the performance for DSP algorithms that are frequently implemented in FPGAs, with reduced power consumption and unit IC costs that are 30-50 percent lower.

The Customizable Atmel Processor (CAP) devices will be extensions of Atmel's existing 32bit ARM7-, ARM9, ARM11 AVR32UC3- and AVR32 AP7-based MCU families. Like all Atmel's 32bit MCUs, AT91CAP MCUs include an Atmel processor core, a variety of peripherals (each with its own DMA) and multiple high-speed buses.

The AT91CAP devices include a metal programmable block (MP block) with up to 2 million FPGA-equivalent gates that can be used to implement one of a variety of functions. These include DSP algorithms or other IP commonly implemented in FPGAs, one or more additional processor cores or additional peripherals not currently available on standard product.

Atmel's ARM7- and ARM9-based MCU families are the first to add customizable versions, the AT91CAP7 and the AT91CAP9. Any existing ARM7/9-plus-FPGA design can be migrated to an AT91CAP device. Even with high degree of customization in an AT91CAP device, the NRE is only $150,000 including mask, engineering charges and prototypes. There are no license fees or royalties charged for the ARM cores in the CAP devices.

Worst-case static power consumption is 3-4mW, only 0.2 percent of the nearly 2W consumed by a typical FPGA. Depending on the design and application, the dynamic power consumption of logic in a CAP-enabled device can be as low as one-tenth of that in an FPGA.

Unit costs for Atmel's CAP MCUs are typically 30-50 percent lower than those for a standard product ARM-plus-FPGA combination. Prices for the ARM7-based AT91CAP7 start at $5.44 in quantities of 50,000 units. The ARM9-based AT91CAP9S is priced at $13 in quantities of 100,000 units.

Faster DSP algorithms
External FPGAs, which are frequently used to accelerate DSP or other functions have slow clocks that rarely exceed 50MHz for the bulk of their logic. On- and off-chip delays from external devices further compromise system performance.

The logic in the MP block on Atmel's CAP devices is metal-programmable and thus has more efficient routing and requires fewer transistors to implement the same logic as an SRAM-based reprogrammable FPGA. The smaller number of transistors reduces both silicon area and power consumption, while also minimizing logic delays.

By integrating a system's unique IP and glue logic on-chip with the MCU, Atmel has eliminated associated on- and off-chip delays. The logic on AT91CAP devices can be run at full bus speed with zero wait states. Moreover, the MP block can achieve clock rates of 400MHz or more, increasing performance of FPGA logic implemented in the MP block by 8 times.

AT91CAP-enabled MCUs have a multilayer bus matrix with multiple bus masters dedicated to the MP block that eliminate bus contention and maximize on-chip bandwidth. AT91CAP7 has a six-layer bus with four bus masters dedicated to the MP block for maximum on-chip bandwidth of 19.2Gbps. The AT91CAP9 has a 12-layer bus with three bus masters dedicated to the MP block for a 38.4Gbps maximum on-chip bandwidth.

Multicore implementation
The MP block on CAP9 was designed to enable the implementation of a second ARM926EJ-S core with caches and it can also implement an AVR32 core or multiple 8bit cores, allowing designs with multiple MCUs to be completely integrated on an SoC. For example, sensor-rich industrial control systems frequently require 8bit MCUs for each sensor in the system. Multiple 8bit MCUs can be integrated on a CAP-enabled device, reducing cost, power consumption and system complexity. Bus master controls and DMA access can be provided between the MP block and the system bus to provide maximum connectivity for additional processors.

Designers requiring an MCU with a unique peripheral set, not available on any standard product MCU may implement them in a single-chip CAP MCU. Atmel has extensive libraries of well-documented peripherals that include TWI, SPI master and slave, SSC, MCI, USARTS, Ethernet MAC, CAN, EBI, full-speed USB host and device, image sensor interface, LCD and AC97 controllers, timer counters, ADCs and AES/TDES encryption/decryption engines. There is no extra charge for including Atmel peripherals on CAP devices. Customer may also implement their own or third-party peripherals in the MP block.

DMA on all peripherals
As with all Atmel's 32bit MCUs, nearly every peripheral on a CAP MCU has its own DMA, supported by a up to 24-channel peripheral DMA controller (PDC). The PDC off-loads data transfers between the peripherals and memories from the CPU so data transfers that completely overload conventional ARM7 (4Mbps) or ARM9 MCUs (20Mbps with caches) can be effected with 95 percent of processor cycles still available for application processing—increasing processor throughput in high bandwidth applications. Multiple DMA channels in the MP block are available to connect the application-specific peripherals and interfaces to the PDC.

All CAP devices also have Atmel's system controller with an 8-level, priority, vectored interrupt controller, as well as reset, startup/shutdown, timing, power management, parallel I/O control and debugging.

MCU offerings
Based on the ARM7TDMI processor core, the AT91CAP7S MCUs offer customizable logic equivalent to approximately 28,000 or 50,000 FPGA LUTs or 250,000 or 450,000 routable ASIC gates. Peripherals include USB device, SPI master and slave, two USARTs, three 16bit timer counters, an 8-channel/10bit ADC, plus interrupt control and supervisory functions. Target markets for AT91CAP7 include industrial, medical and automotive. Moreover, the fabless semiconductor space may realize major benefits from AT91CAP7 in easily creating derivative products.

Developed for deeply embedded, networked systems with man-machine interfaces, the ARM9-based AT91CAP9S integrates a 200MHz ARM926EJ-S core with 16Kbytes each of program and data cache, and customizable logic equivalent to approximately 28,000 or 56,000 FPGA LUTs (250,000 or 500,000 routable ASIC gates). It also has 32Kbytes of additional SRAM, 32Kbytes of ROM, external bus interface (EBI) with error correction code (ECC) for NAND flash/SmartMedia, two buses are dedicated to data- and instruction-memories that bypass the cache to accommodate deterministic operation, called Tightly Coupled Memories (TCM).

AT91CAP9S peripherals include both a USB full-speed host and USB 2.0 high-speed device, 10/100 Ethernet MAC, image sensor interface, 2.0A and 2.0B CAN controller, LCD controller, MCI, SSC, PWM, LCD and AC97 controllers, SPI master and slave, two USARTs, three 16bit timer counters, and an 8-channel, 10bit ADC. AES/TDES encryption/decryption engines are optional in AT91CAP9SC version.

Eleven buses on the AT91SAM9CAP provide multiple parallel on-chip data transfer channels and a total on-chip bandwidth of 41.6Gbps.

Design migration
Moving from an existing ARM7- or ARM9-plus-FPGA design to a CAP-enabled MCU can be as simple as providing Atmel with the RTL netlist, which Atmel implements in the MP block in the CAP-enabled MCU. HDL code for the application-specific DSP algorithms or other custom logic for new designs can be developed, debugged and verified in parallel with MCU code using Atmel's AT91CAP9-DK development board and standard third-party FPGA design tools. Code from designs done with any ARM7- or ARM9-based MCUs can be ported to the CAP device. Atmel will integrate royalty-free peripherals from its extensive IP library, free of charge. Royalty-based IPs from third parties are also available depending on license arrangement.

Prototypes are available within 10 weeks of final gate level netlist and production quantities within 16 weeks.