Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

A new way to predict LDMOS DC signal behavior

Posted: 29 Jun 2007 ?? ?Print Version ?Bookmark and Share

Keywords:wireless design? Verilog model? LDMOS DC behavior?

By Amedeo Michelin Salomon, Giuseppe Privitera

Due to its cost effectiveness and high performance, LDMOS devices are widely used in RF applications, ranging from digital communication infrastructure (cellular base stations) to low-cost portable radios (private mobile radios), commonly known as Walkie-Talkies.

To reduce the design cycle time and cost for such wireless applications, it is useful to have models that can help RF engineers predict and simulate the behavior of RF power transistors, especially concerning large-signal behavior.

New solution
The model discussed in this article is simple in concept and describes with good approximation the DC, small-signal S-parameter and large-signal behavior. This model has been implemented in the Agilent Advanced Design System, in Verilog language and includes the parasitic elements of the package, as well as a thermal node that takes self-heating effects into account.

This article will briefly describe how to extract the model parameters for the PD54003L-E device, which is a 3W, 7.2V, 500MHz LDMOS housed in a PowerFLAT plastic package (5-by-5mm). As an internally unmatched device, PD54003L-E can be used in portable applications over HF, VHF and UHF frequency bands. At the end of the article we will validate this new model using ST?s DB-54003L-175 demo-board, especially designed for two-way portable radio applications using PD54003L-E over the 135-175MHz frequency band.

The model introduced is a behavioral model with the equations written in Verilog language. By observing the equivalent model schematic of Figure 1, parasitic elements associated with the device, nonlinear current generator, JFET resistance and substrate-body diode elements can be noticed.

Parasitic elements - To model the parasitic elements of the device, a resistance and an inductance are placed in series at each terminal. The model can change the resistance and inductance values according to the simulation temperature.

Parameter P in Formula 1 is the temperature dependence, where Tc is its temperature coefficient, T is the temperature used in the simulation and Tnom is the temperature used to measure the parameter value.

Nonlinear current generator - The nonlinear current generator controlled by Vgs and Vds is the most important factor used to calculate the static and dynamic current of the device. Moreover, the static current is required to define the working region of the MOS.

Table 1 reports all the parameters required to extract the equations of the current generator. To get the generator current equation, a set of equations must be defined. An important parameter to consider is the threshold voltage of the device shown in Formula 2.

Moreover, a new threshold voltage formula is necessary to describe the weak and strong inversion region in a single equation (Formula 3).

To describe both regions, a new gate voltage can be defined, as in Formula 4. Another important parameter to define is the gain factor with zero bias. Referring to Formulas 5, 6 and 7, the gain factor degrades according to the Vgs voltage (mobility degradation). Formulas 8 and 9, which define the drain saturation voltage, complete the set of equations needed to define the generator current (Formula 10 and 11).

The automatic ADS optimizer was used to extract the parameters for the current generator. The threshold voltage and the gain factor have been extracted from the input characteristics with Vds at a low voltage level. Concerning mobility degradation, the transconductance parameter was used varying Vds and with Vgs at a high voltage level. The sub-threshold voltage was extracted from the input characteristics with a gate voltage level below the threshold voltage level.

L is the physical channel length of the MOS, while L0 influences the output conductance which depends on KE and EPS. DEL and DELVG affect the VDSAT and are extracted from the output characteristics in the saturation region. As mentioned, all the equations have been implemented in Verilog language.

JFET resistance - The quasi-saturation region is modeled by a nonlinear JFET resistor. The mathematical empirical equation is defined in Formula 12, where pres depends on the current and on the drop voltage across Rj.

Useful to delete any convergence problem, Figure 2 shows the resistor law for the variation of Vds (using the right hand function approach) (Formula 13). A similar graph and function can be obtained by varying Vgs.

The function g(pres) was created to bind the Rj to the current Id. This is accomplished by introducing a new parameter linked to the dissipated power on Rj (Formula 14), where pres is linked to the dissipated power on Rj through RPWR.

h(T) (Formula 15), introduces the temperature dependence of Rj, where TCR1 and TCR2 are temperature coefficients in the linear region.

Rj is extracted from the DC output characteristics in the linear region with high bias current.

Substrate-body diode - The body-substrate diode is employed to describe the breakdown, the drain current leakage and the capacitance between the drain and source.

The thermal variations are shown by Formula 16. To include the temperature in the saturation current refer to Formula 17. The diode current is implemented in Formula 18, 19, 20, 21 and 22. The charge equation is given by Formula 23.

The remaining model parameters are the capacitances Cgs and Cgd of the MOSFET. The gate-source capacitance is modeled with a constant capacitance, because it is related to a highly doped MOSFET (Formula 24).

Moreover, the gate-drain capacitance can be considered as a classic MOSFET model capacitance, where the equations of the charged capacitance (Formula 25, 26, 27 and 28) can be divided into four regions (Figure 3). Even in this case, capacitance variation depends on temperature (Formula 29).

To extract the capacitance variables, a classic configuration has been used to measure the Ciss, Coss and Crss.

Thermal node - A "thermal node" has been introduced to consider the self-heating effect (Figure 1). The voltage between the external thermal circuit port and the source node is related to the junction temperature rise. The current source of the circuit is equal to the dissipated power.

In this first model implementation, we have not considered the temperature dependent variables.

Package simulation
To include all the parasitic elements of the package in the model, several electromagnetic simulations were performed.

Figure 4: The gate-drain capacitance can be considered as a classic MOSFET model capacitance, where the equations of the charged capacitance can be divided into four regions.

The simulated package (PowerFLAT), including the internal structure of the device, takes into consideration the leads, the paddle, wire bonding and the pad on the silicon. A typical package structure for LDMOS transistors is represented in Figure 4.

Observing the internal structure, three of the four pins on each side are shorted together through a copper bar (Figure 6). The bonding wires connect the external pins to the gate and drain pads of the device (Figure 5).

The molding resin has a dielectric constant equal to 4 and a dielectric loss tangent of 0.005. The leads of the package are made of copper, while the bonding wires are made of gold.

Figure 5: In this PowerFLAT cross-section, the bonding wires connect the external pins to the gate and drain pads of the device.
Figure 6: Three of the four pins on each side are shorted together through a copper bar

During simulation, the device contact pads and the paddle are considered as a PEC (perfect electric conductive surface lossless). Instead, along the external sides of the air box containing the package, an electric and magnetic field total wave absorption condition was set to consider the radiation losses (Formula 30).

During the simulation, lumped ports were used to excite the fields (Figure 6). The package simulation performed was in the frequency range from 1MHz to 50GHz.

To minimize the simulation time and increase accuracy, the structure was split into two parts (drain and gate). In this way, the reciprocal coupling between the input and output parts are not considered. To take into account such effect, an extra capacitor (Cgd-package) has been used. To complete the package model, an extra inductor (Lvia) associated with the source has been added. This inductor represents the effect created by the "via holes". The S-Parameters concerning the electromagnetic simulation of the gate section of the package are shown in Figure 7.

Figure 7: The S-Parameters concerning the electromagnetic simulation of the gate section of the package.

Moreover, using the measured S-parameters of the packaged device, it was possible to extract the Cgd-package and the Lvia. Looking at Figure 8, it is possible to see the circuit representing the union between the package model and the device model.

DC and RF small signal validation
Figure 9, Figure 10 and Figure11 compare the measured DC and RF small signal parameters with the simulated parameters (Ciss, Coss, Crss, low signal S-parameters and input and output dc curves). The simulations predict with good approximation the above mentioned parameters, including S21 and S22 which are the most difficult to predict.

Figure 10: Measured S-parameters vs. simulated parameters (Vds = 7.2V; Idq = 100mA.

Large signal validation
Using the ADS with harmonic balance engine simulator, the model has been simulated in conjunction with the DC network and the input and output matching network of ST's demo-board DB-54003L-175 (Figure 12). The DB-54003L-175 demo-board was developed to demonstrate the best broadband performance of PD54003L-E.

In the harmonic balance simulations, we used all the information relative to the board and the S-parameters of the lumped capacitors and inductors.

Figure 12: ST's demo-board DB-54003L-175.

Figure 13 also compares the simulations and measurements of the demo-board at 155MHz, varying the power delivered by the generator at the input port.

Pin is the power available from the generator, Nd is the drain efficiency, input return loss is the ratio between the power reflected from the device and the power available from the generator and gain is the ratio between the power dissipated on the load and the power available from the generator.

Article Comments - A new way to predict LDMOS DC signal...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top