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Low-cost FPGAs prop up GbE, PCIe, RapidIO

Posted: 02 Jul 2007 ?? ?Print Version ?Bookmark and Share

Keywords:FPGAs supporting mainstream interconnects? low-cost FPGAs for bridges and endpoints? Gigabit Ethernet? PCI Express? serial RapidIO?

Greenfield: The entry-level FPGAs will fill a gap.

Altera Corp. has officially rolled out a line of entry-level FPGAs built to support Gigabit Ethernet, PCIe and serial RapidIO transceivers at the lowest possible price for a programmable part.

The Arria GX family handles data rates of as much as 2.5Gbps at costs as low as $50 for a device providing 50,000 logic elements.

The move acknowledges that the three protocols are pushing into mainstream systems in a range of computer, communications and embedded systems. As they do so, the protocols are demanding the lowest possible cost, especially for bridges and endpointsthe target applications for Arria.

"In the last year or so, we have seen these three protocols making the transition to the mainstream," said David Greenfield, senior director for product marketing at Altera. "As the volumes accelerate, there's a new price pressure."

Simply characterizing the company's existing entry-level Cyclone III FPGAs for the transceivers was not plausible because the parts use wirebond packaging without the signal integrity to carry complex gigahertz signals. Thus, to create Arria, Altera streamlined a version of its high-end Stratix II FPGAs that use flip-chip packages for the three protocols.

"There clearly is a cost premium for flip-chip packaging, but the value comes in knowing it will work every time," said Greenfield.

The Arria parts cost as little as one-third that of Altera's Stratix devices, but a slight premium above its Cyclone family. The five members of Arria generally hover at about $1 per 1,000 logic elements.

Greenfield said he believes the new FPGAs will fill a gap. At one end, some engineers use high-end FPGAs with transceivers. At the low end, they typically use FPGAs in wirebond packages with external PHY-layer devices, or an application-specific chip with transceivers but without programmability.

Altera sees PCIe emerging in test, medical and comms systems, far beyond what Intel has established for the protocol in computing, Greenfield said. Gigabit Ethernet is rapidly emerging for use in networking industrial gear, and "as a diagnostic tool, it has become the protocol of choice," he added.

For its part, serial RapidIO is riding the coattails of support on DSPs from Texas Instruments Inc. and Freescale Semiconductor Inc., he said. Arria supports x1 and x4 configurations of PCIe and serial RapidIO.

All the Arria parts typically run at data rates of about 150MHz, though individual blocks, such as DSPs, on the chip can run faster. The parts support 12 transceivers running at 1.25GHz or 2.5GHz.

Arria chips come in five density levels, ranging from 21,580 to 90,220 logic elements. Initially, the devices with 50,000 gates will be the most cost-effective. The devices can accommodate 1.2-4.5Mbits of memory and come in fine-line BGA packages with 484, 780 or 1,152 I/Os.

The chips, made in a 90nm TSMC process, can be programmed using Altera's Quartus II ver 7.1 software. A protocol-specific development kit will also be provided. The first Arria chips have shipped, and all five will reach production in August.

- Rick Merritt
EE Times

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