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Tame signal integrity in the fast lane

Posted: 02 Jul 2007 ?? ?Print Version ?Bookmark and Share

Keywords:signal integrity design? signal routing? EMI problems?

By Abdullah Raouf
Pericom Semiconductor Corp.

As data rates increase, signal integrity becomes the most critical factor for design engineers. This exponential data rate increase can be observed in all applications, from handheld mobile devices and consumer display products to high-bandwidth routers/switches.

Jitter (noise) is the number one cause of reduced signal integrity levels within a design. Instead of implementing signal integrity enhancement techniques with layout, impedance matching and the use of more-expensive materials, design engineers can simply add jitter eliminators, such as equalizers, to their designs. This will allow them to focus more of their effort on their system's core design without having to specialize in signal integrity.

Designing for integrity
Signal routing used to be a simple concept. There was no difference among video signals, voice signals or data signals, from a routing perspective. Consequently, signal routing was seldom a concern. In recent times, however, this has completely changed. Video signals are now traveling at 3.3Gbps per path and data signals are traveling beyond 5Gbps per path. High-speed serial standards such as PCIe, XAUI, SATA, TMDS and Display Port have created a demand for design teams and engineers to not only think about signal integrity but to also have an in-depth knowledge of how it will affect the performance and reliability of today's systems.

To gain this knowledge, engineers must first understand what affects signal integrity within a system. Signal integrity loss is observed within a system by the addition of signal jitter. Two main types of jitter in a system make up the total jitter: random and deterministic. While random jitter is unbounded and Gaussian in nature, deterministic jitter is bounded and predictable. In 90 percent of the systems, the latter type will be the major signal integrity issue with which design engineers must deal.

Figure 1: Signal loss is associated with different FR4 trace lengths and frequencies.

Deterministic jitter encompasses intersymbol interference, (ISI) duty cycle distortion and periodic jitter caused by bandwidth limitation problems, asymmetries in clock cycles and cross-coupling or EMI problems, respectively. Passive components such as connectors, PCB trace, long cables or other passive components along the trace contribute the most to deterministic jitter.

A signal is attenuated more at higher frequencies. Such causes a power level mismatch within a given data stream and this power level mismatch causes ISI within your signal. ISI could reduce signal integrity enough to prevent the receiver from extracting any real data from the signal at the receiving end.

The reason for the power level mismatch is that no design engineer can guarantee the data traveling through his or her design. The data could be transitioning 100 percent of the time (0-1-0-1-0-1), or it could be a constant nontransitioning (1-1-1-1-1-1) cycle. It is clearly understood that the observed duty cycle of the six transitioning bits described above is 6x smaller than the constant stream of six consecutive 1's. Since the duty cycle is 6x smaller, the frequency is 6x larger. And if your data stream contains both types, you can have a signal at the end with very different power levels, since the higher frequency will be attenuated more.

Fixing power mismatch
Most high-speed signal standards have defined specifications that can minimize the number of nontransitioning consecutive bits, such as 8B/10B encoding. This encoding scheme ensures that a data stream never has more than four consecutive nontransitioning bits. However, it still leaves a design engineer prone to a signal with a section that has 4x as much power at the received end of the trace.

To compensate for that mismatch in power level and to reduce ISI, designers could use equalization or de-emphasis techniques. Equalization produces a power boost to all high-speed bits. This enables the high-speed bits to have power levels that are similar to the lower-speed bits, thereby minimizing the power level mismatch.

Figure 2: Signal integrity measured with equalization (top) and without equalization (bottom), both after 25m of cable length.

De-emphasis, which is the opposite of equalization, also has the same objective: Minimize the power-level mismatch. This is done by reducing the power of the low-speed bits, however, while equalization increases the power of the high-speed bits. Also, de-emphasis works only on the transmitted bits while equalization works only on the received bits.

This is not the only technology that can be used to eliminate deterministic jitter. The user will most likely require some sort of transmitter jitter eliminator, such as de-emphasis (as described above). For a true jitter-elimination scheme, both circuits will be required.

Don't allow jitter to compromise your design, as low-cost signal conditioning solutions are readily available. Design-in the equalization and de-emphasis circuitry required to eliminate the jitter caused by long FR4 traces, connectors and long cables, and you will not have to worry about understanding the details of signal integrity enhancement techniques. Let the jitter terminators deal with that!

About the author
Abdullah Raouf
is a product-marketing manager for Pericom Semiconductor Corp.'s signal integrity enhancement solutions for digital video signals. He holds a BS degree in Electrical Engineering from the University of California, Davis.




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