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Synopsys, UMC partner on 65/90nm connectivity IP

Posted: 05 Jul 2007 ?? ?Print Version ?Bookmark and Share

Keywords:mixed-signal IP? network connectivity? PHY IP?

Synopsys Inc. announced it has teamed with United Microelectronics Corp. (UMC) to port the Synopsys DesignWare USB 2.0, PCIe, serial ATA and XAUI PHY semiconductor intellectual property (IP) to UMC's 90nm and 65nm technologies.

The DesignWare PHYs are highly complex, process-tuned analog interfaces used in high-volume, high-value consumer, computer, storage and networking SoCs. The DesignWare PHY IP provides 90nm and 65nm implementations of popular high-speed derail communications protocols, helping reduce risk, speeding time-to-market and ensuring a more predictable path to silicon success.

The USB 2.0 nanoPHY for USB 2.0 is a mixed-signal IP core that is ideal for USB applications that require low power, small area and PHY tunability. Combined with the DesignWare USB Device, Host and On-The-Go controllers and verification IP, Synopsys' DesignWare USB IP provides designers with an easy-to-integrate, interoperable USB IP solution that can be quickly implemented into next-generation applications.

The DesignWare PHY IP for PCIe, XAUI and serial ATA, combined with the respective DesignWare digital controllers and verification IP, delivers a complete set of IP solutions for these protocols. The PHY IP offers the lowest power (30-50 percent lower than competitive solutions), high performance margins and small die area. In addition, the ATE test vectors and a unique built-in diagnostic engine enable at-speed production testing of the mixed-signal PHYs. The associated DesignWare verification IP enables a quick and efficient way to verify PCIe designs using the latest functional verification methodologies.

"Many of our customers are seeking standardized interface IP for the USB, PCIe, serial ATA and XAUI protocol standards," said Chingchi Yao, senior director of customer design support at UMC. "Synopsys' high-value cores are poised to allow chip designers to quickly obtain and integrate critical functionality into their designs and then ramp into volume production. We are taking an aggressive position in making reduced-risk IP available for leading-edge designs and are among the first companies to have Synopsys port their newest portfolio of mixed-signal IP to 65nm processes."

"Synopsys continues its track record of providing customers with integrated, high quality IP solutions that support the latest process technologies," said John Koeter, senior director of marketing for DesignWare IP at Synopsys. "By working closely with UMC on developing the DesignWare IP in UMC's 90nm and 65nm processes, we are working to enable our mutual customers to achieve first-pass silicon success."

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