Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > Manufacturing/Packaging
?
?
Manufacturing/Packaging??

Understanding flip-chip and chip-scale package technologies and their applications

Posted: 10 Jul 2007 ?? ?Print Version ?Bookmark and Share

Keywords:flip-chip package? chip-scale package? IC packaging? wafer-level packaging?

The advance in semiconductor technology has created chips with transistor counts and functions that were unthinkable a few years ago. Portable electronics, as we know it today, would not be possible without equally exciting developments in IC packaging. Driven by the trend towards smaller, lighter, and thinner consumer products, smaller package types have been developed. The smallest possible package will always be the size of the chip itself.

Driven by the trend to smaller, lighter, and thinner consumer products, smaller package types have been developed. Indeed, packaging has become a key determinant for using or abandoning a device in a new design. This article first defines the terms "flip chip" and "chip-scale package" and explains the technical development of wafer-level packaging (WLP) technology. Next it discusses practical aspects of using wafer-level packaged devices. Topics in that discussion include: determining the availability of flip-chip/UCSP packaging for a given device; identifying a flip chip/UCSP by its marking; the reliability of wafer-level packaged parts; and finding applicable reliability information.

Please view the PDF document for more information.




Article Comments - Understanding flip-chip and chip-sca...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top