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RTL synthesis tool eases chip-level interconnect design

Posted: 11 Jul 2007 ?? ?Print Version ?Bookmark and Share

Keywords:chip-level interconnect design? RTL synthesis? floorplanning tool?

Claiming a new "design with physical" approach that helps solve problems with chip-level interconnect, Cadence Design Systems this week plans to announce a new component of its Cadence LogIC design Team Solution. It integrates the Encounter RTL compiler synthesis tool with the First Encounter floorplanning tool so that synthesis can get timing estimates from physical floorplanning data.

The solution is aimed at the 10 percent of wires that represent chip-level interconnect. But that's no small matter, according to Cadence, because these long wires are the hardest to predict and show the greatest variations.

Solutions already exist for timing prediction for the 90 percent of wires that represent local interconnect, such as Cadence's own physical layout estimation (PLE) technology, but the longer chip-level interconnect wires generally require placement or floorplan data, according to the company.

New design methodology
Rather than taking synthesis down into the physical design process, the "design with physical" component of the Logic Design Team Solution aims to bring floorplan data up into RTL synthesis. "Rather than making the logical designer do physical design, or the physical designer do logical design, we're trying to bring the right amount of information from one world into another," said Jack Erickson, product marketing director for Cadence's Encounter group.

It's very different, Cadence representatives said, from physical synthesis, which combines synthesis with placement and generally starts at the netlist level. "Physical synthesis, historically, is used by layout engineers," said Eric Filseth, corporate VP of product marketing for Encounter at Cadence. "We're building a logic designer environment."

Filseth also said physical synthesis focuses on short, local interconnect wires. "To do the 10 percent of the wires in the design that are long wires, you had to have a floorplan, and it had to be done by a back-end designer," he said.

With Cadence's new approach, First Encounter's virtual silicon prototyping capability is incorporated into the synthesis cockpit to allow users to quickly obtain a view of physical interconnect timing. A single command, "predict_qos," runs First Encounter and back-annotates physical timing information into the synthesis process. A cross-referenced graphical debug environment provides a communication bridge between the logic and physical design teams.

"The synthesis user can stay in the synthesis environment and get physically accurate timing back-annotated into that environment," Erickson said.

First, a floorplan
Filseth acknowledged, however, that First Encounter is primarily used by physical designers today. While an RTL synthesis user can automatically generate a floorplan, it's best if an experienced First Encounter user first creates a floorplan that's loaded into the synthesis tool.

Pradeep Fernandes, vice president and general manager for synthesis solutions at Cadence, said First Encounter's timing estimates are within 5-10 percent of silicon and users have some control over speed and accuracy tradeoffs. That accuracy is close enough to let users make global changes. "More than absolute numbers, we need to take continuous refinement into account," Fernandes said.

The "design with physical" component of the Cadence Logic Design Team Solution, which includes the latest release of the Encounter RTL Compiler and the integration with First Encounter, is available now.

- Richard Goering
EE Times




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