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Cadence, STARC team to address 65nm DFM issues

Posted: 12 Jul 2007 ?? ?Print Version ?Bookmark and Share

Keywords:65nm design flow? 65nm DFM issues? advanced design flow?

Cadence Design Systems Inc. and Japan-based Semiconductor Technology Academic Research Center (STARC) have partnered to deliver an advanced design flow to improve manufacturability and yield for 65nm designs.

The flow is based on the Cadence Encounter digital IC design platform and provides STARC member companies with integrated and enhanced DFM and design-for-yield capabilities. It delivers a comprehensive methodology to address 65nm design issues while minimizing potential yield fall-out due to tighter manufacturing parameters and effects due to lithography and chemical mechanical planarization.

"Through our collaboration with Cadence, we believe we can help our member companies address their most pressing DFM issues at 65nm," said Nobuyuki Nishiguchi, VP and general manager of Development Dept.-1 at STARC. "Because the flow is based on the integration of key DFM technologies into the Encounter platform, our member companies will be able to improve yield while still meeting aggressive power, performance and schedule requirements."

"Many of our key customers in Japan depend on STARC and Cadence to help address some of their most pressing design issues," said Eric Filseth, corporate VP of marketing at Cadence. "Our work with STARC will allow them to deliver a comprehensive design flow that addresses the DFM challenges at 65nm, and we look forward to similar collaborative efforts at 45nm and beyond."

STARC members are top-tier Japanese companies Fujitsu Ltd, Matsushita Electric Industrial Co. Ltd, NEC Electronics Corp., Oki Electric Industry Co. Ltd, Renesas Technology Corp., Rohm Co. Ltd, Sanyo Semiconductor Co. Ltd, Seiko Epson Corp., Sharp Corp., Sony Corp. and Toshiba Corp.

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