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XMOS fields software-defined silicon

Posted: 12 Jul 2007 ?? ?Print Version ?Bookmark and Share

Keywords:multithreaded processor architecture? parallel processing? multicore? consumer electronics?

May: What are the options today in multiprocessing architecture?

Fabless semiconductor startup XMOS Semiconductor Ltd is the latest company trying to deploy a multiprocessing architecture, but if pedigree is anything to go by it has more chance of success than many others.

The company is the route to market for the ideas of its chief technology officer David May. Back in the 1980s, May was the architect of the transputer!a processor designed specifically for parallel processing!and the author of its accompanying Occam programming language. Before founding XMOS in July 2005, May was the head of computer science at Bristol University having spent a number of years in academia, prior to which he spent 16 years in the semiconductor industry with STMicroelectronics and Inmos. Inmos was where May did his transputer work.

Not surprisingly, the XMOS architecture has similarities to the transputer but recast in an approach designed to make use of what 20 years of Moore's Law have made possible!multicore single-chip implementation.

Other approaches to monolithic parallelism have been many and varied, but not always successful. They have included: superscalar and multithreading uniprocessors, very long instruction word (VLIW) processors, multiple processors on a die linked in an FPGA-like fashion and the concept of marrying a housekeeping processor with a reconfigurable FPGA-like fabric.

Event-driven, multithreaded design
XMOS has chosen an event-driven, multithreaded processor that will be deployed in two-dimensional arrays in a family chips due for introduction in 2008. The processor, the 32bit XCore, has a fixed instruction set developed for fast real-time response and low silicon cost. The integration of pin-control within Xcore coupled with an inter-core communication link named XLink allows complete systems, including interfaces, to be implemented in software. Product development uses a unified embedded software flow founded on C-based programming languages.

Any success achieved by previous monolithic parallel processors has usually required the tailoring of the hardware to a narrow set of applications. Attempts to produce general-purpose architectures have been thwarted by problems inherent in programming parallel resources with the popular but concurrency-lacking C language.

Figure 1: Not surprisingly, the XMOS architecture has similarities to the transputer but recast in an approach designed to make use of what 20 years of Moore's Law have made possible!multicore single-chip implementation.

May and XMOS, possibly learning from experience with the elegant but under-used occam, have tried to come up with the best of both worlds with an architecture that can be programmed from C or C++ but with an additional language 'XC' that can be used for greater control of multithreading capability and I/O ports.

Conventional development
By harnessing together the appropriate compilers for C++, C and XC and a linker that brings the compiled code together, the architecture looks much like a conventional processor from a development point of view, according to Noel Hurley, VP of marketing. Arrays of processor devices will allow system functions that would normally be implemented in hardware to be defined in software, unifying the design flow for software and hardware, the company said in its documentation.

In fact no RTL or lower level hardware design skill is necessary to work with the XCore. It just requires an embedded software approach using C-based languages to implement interfaces, algorithms and general software. As a result companies will be able to innovate and differentiate their silicon without waiting for ASIC developments or ASSP spins, the company claimed.

"We simulate all hardware functions from I/O to DSP. We unify the design flow, there is one description language that combines hardware and software," said Hurley. "You make decisions about whether things are done in parallel for performance or serially for silicon efficiency but you can delay the decision until the very last minute."

In 90nm CMOS a single XCore offers approximately 500MIPS of control software performance, 7MSPS performance on a 16-tap FIR filter and 200Mbps communications.

Software-defined silicon
James Foster, CEO of XMOS, said he expects the company's chips to be successful in areas where FPGAs have found success due to their configurability, such as communications base stations and switching fabrics. But Foster added that XMOS silicon would also get design wins in consumer electronics goods and even in such high volume devices as mobile phone handsets.

XMOS describes its approach as "software-defined silicon" and reckons it will provide consumer electronics system designers with the unit cost advantage of the SoC!but without the development time and costs!combined with the flexibility of the FPGA!but with far better silicon efficiency. The developer can write code to dynamically partition resources between control processing, DSP processing and I/O processing, all on mass-produced chip of silicon. "Around $1 for complete flexibility," is the boast on the company's presentation materials.

May said: "What are the options today? An ASIC's NRE cost means it's too risky and expensive in all but the highest volumes. The rigidity of ASSPs means design freedom is limited and real creativity is effectively strangled. Finally, FPGA's high complexity in programming and cost of silicon prohibits their use in high-volume consumer electronics."

There is still an issue of how transportable the compiled code is across different implementations of the XMOS architecture with more or less resources.

Figure 2: XMOS has just taped out its first product design based on its new architecture.

"The programmer does not need to be aware of which processors are running. He or she allocates tasks to threads. That allocation is done manually," said Hurley. "There are 8-theads per core, there should be more threads than tasks."

Hurley's response begs a question about the power efficiency of the architecture. Burning power during "no-ops" has been one the perennial problems of VLIW machines and parallel processors and in more advanced silicon leakage current alone is a significant power drain.

More tricks to come
XMOS is not revealing all the information about its architecture and implementation right now, keeping some things back for a product announcement to come in 2008. "This is an event-driven processor, it is optimized for no-ops," said Foster. If threads are not being pushed through it will consume little power and we are using mixed Vt [threshold voltage] libraries," he added.

Having developed its architecture in System C and demoed it on an FPGA, XMOS has just taped out its first product design, which is being made for the company by foundry Taiwan Semiconductor Manufacturing Co. Ltd in 90nm CMOS. The company will be offering chips, software IP and development tools and its first product is due to be announced during the first quarter of 2008.

- Peter Clarke
EE Times Europe




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