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Verify designs with assertions

Posted: 16 Jul 2007 ?? ?Print Version ?Bookmark and Share

Keywords:assertion-based verification for RTL? ABV methodology? verify design assertion?

Recent standards for assertions and newer verification methodologies have eased the designer's ability to create, implement and monitor assertions. The use of assertions in formal, simulation and acceleration/emulation is accelerating as users see the tremendous benefits that can be gained by having assertions actively monitor their RTL code for errors.

With a complete assertion-based verification (ABV) methodology, designers write assertions as they develop the RTL. These assertions, along with automatically extracted assertions, are then verified using formal analysis on the individual blockssometimes months before simulation.

At the integrated block or cluster level, formal analysis continues to be useful as a complement to simulation. At this level, simulation helps to verify not only the correctness of assertions, but also the functional coverage of the entire block or cluster.

Finally, at the full-chip or system level, simulation, acceleration and emulation are the primary tools of choice. The same assertions used in the sub-blocks that make up the full chip provide continuous benefits in observability. At this stage, assertions will deliver faster debug and better corner-case exposure rates, and contribute to functional coverage metrics.

When adopting components of ABV into standard production flows, teams do run into various challenges. Here are some tips and tricks with ABV:

Do

  • Focus on a productive subset of the assertion language. Biting off more than you can chew can increase your chances of making mistakes. There is no reason to become proficient on the entire assertion language right off the bat. There are plenty of benefits to an incremental approach, such as easier adoption and higher return-on-investment.

  • Consider using a library. Libraries such as Open Verification Library and Incisive Assertion Library contain common components and design constructs that make it easy to get started with ABV. Many companies have achieved great returns from a limited set of assertion library elements as the starting point.

  • Consider the big picture. Work done on and with assertions should be leveraged across the entire flow. This includes designs, block, chip and full system. For example, assertions written for formal analysis should be leveraged in simulation and again later, for acceleration and emulation. Doing so makes the overall methodology more fluid, repeatable and successful.

  • Consider reuse. For common interfaces within your design, think about creating a reusable library of components that are parameterizable. Reuse these again and again within a project or in future projects.

  • In simulation, complement your assertions with coverage. Most assertions describe the functionality of the design and say nothing about how good the stimulus stressing the design/assertions is. Writing some assertions to serve as functional coverage targets can help.

Don't

  • Spend much time worrying about which assertion language to use. System Verilog Assertions and Property Specification Language are just plain syntax, providing virtually the same capability while differing from a HDL. Both assertion languages represent a completely new language and syntax, and will add to the overall learning curve.

  • Corner yourself into one language. In reality, assertions may come from multiple places (third-party verification intellectual-property providers, internal design and verification groups) that leverage multiple assertion languages.

  • Write assertions for all aspects of your design. Focus on areas that are considered higher risk, adding more assertions cautiously, as time permits. Focus on the control logic first. Gaining white-box visibility into the control-oriented portions of your design, which typically will have the most bugs, will yield the highest value.

  • Be afraid to simplify by using simple VHDL or Verilog/SV to generate easier and more familiar conditions to check. This will reduce risk that can arise from creating incorrect assertions. Remember, this code is for simulation only and will not be synthesized.

  • Wait to introduce assertions. Assertion creation should start very early in the design development process, as designers write the RTL verification. Engineers should use assertions and write additional assertions at the block level, and consider end-to-end transactions, complementing designers' white-box assertions.

- Chris Komar
Incisive Core Competency Senior Technical Leader

Michal Siwinski
Incisive Director

Cadence Design Systems Inc.




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