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TI clock generators offer low jitter performance

Posted: 16 Jul 2007 ?? ?Print Version ?Bookmark and Share

Keywords:TI clock generators? low jitter performance? PLL clock generators?

Texas Instruments Inc. has introduced a family of highly programmable, one-to-four PLL clock generator devices with the capability to generate up to nine output clock sources from a single input frequency. The CDCE9xx and CDCEL9xx family of clock generators deliver very low jitter at 60ps typical for consumer applications.

The CDCE9xx devices provide either 2.5V or 3.3V outputs, while the CDCEL9xx provides 1.8V outputs, enabling the low-power capability needed for portable devices. Each PLL supports spread-spectrum clocking (SSC) to reduce EMI for compliance with EMC regulations.

Each output can be programmed in-system for any clock frequency up to 230MHz. These features provide a number of system benefits such as reduced power consumption, shorter lead time and the flexibility to easily upgrade the clock without redesigning the system, said TI. Consumer applications include IP STBs or phones, digital media systems such as DTVs, streaming media and printers, navigation systems and portable devices.

In addition, the clock generator family provides a variety of programmability options including the ability to program and customize the devices in-system through I?C and an EEPROM. By offering footprint compatibility across the family, designers can adapt the system design easily without changing hardware, which reduces cost and enables the designer to simply increase or decrease the number of clock outputs, said TI. The devices further simplify system design by replacing a number of components in the system including crystals, oscillators, buffers and PLLs.

The clock devices are optimized to work with TI's DaVinci-based processors by generating any audio, video, processor or interface clock to drive the digital processor, audio DAC or codec and Ethernet or USB controller. The on-chip voltage-controlled crystal oscillator allows frequency synchronization of different data streams.

The device family is composed of CDCE949 (2.5/3.3V with four PLLs), CDCE937 (2.5/3.3V with three PLLs), CDCE925 (2.5/3.3 V with two PLLs), CDCE913 (2.5/3.3 V with one PLL), CDCEL949 (1.8V with four PLLs), CDCEL937 (1.8V with three PLLs), CDCEL925 (1.8V with two PLLs) and CDCEL913 1.8V with one PLL).

The CDCE949 is available now in a 24-pin TSSOP package and is priced at $2.20 in quantities of 1,000. The remaining devices in the family will be available throughout 2007 in 20-pin, 16-pin and 14-pin TSSOP packages. Evaluation modules are available.

- Gina Roos

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