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DSP promises 112 GMACs of compute performance

Posted: 17 Jul 2007 ?? ?Print Version ?Bookmark and Share

Keywords:FPGA design? multiple cores? high-end signal processing application?

Stream Processors Inc. (SPI) is sampling the latest member of its Storm-1 DSP family, the SP16HP, which provides a cost-effective, easy-to-design, C-programmable alternative to FPGA and multi-DSP designs in digital imaging, video and wireless infrastructure applications.

SP16HP offers 112 GMACs (16bit) or 448 GOPS (8bit) of compute performance in a single chip with a power-efficiency of less than 0.1mW per MMAC.

According to SPI, developing applications in C for SP16HP shortens design times from months to weeks compared to the hardware-oriented methodology used in FPGA designs.

Based on SPI's Stream Processor Architecture, SP16HP provides a single-core programming model, eliminating the pitfalls of having to partition, synchronize and load-balance threads across multiple cores. The RapiDev compiler directs data movement by allowing predictable and optimal application performance and removes the need for assembly coding and manual management of caches and DMA.

"Many developers today have resorted to PCs to run their high-end signal processing applications because they are unfamiliar with multi-DSP or FPGA coding methodologies," said Bill Dally, Stanford professor and SPI co-founder. "SPI allows these users to move to an embedded platform using familiar C-programming tools and accelerate their application performance with lower power consumption."

The chip is housed in a 31mm x 31mm FCBGA package and is implemented in 130nm standard CMOS process. Full production will commence in Q3. Pricing starts at $149 in quantities of 10,000 units.

- Ismini Scouras

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