Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > T&M

Commentary: Imagination turns to reality in verification

Posted: 23 Jul 2007 ?? ?Print Version ?Bookmark and Share

Keywords:verification process? verification innovation? automated management?

By Hamilton Carter
Cadence Design Systems

Imagine if chip designs could always tape out on schedule. Envision engineers not being completely burned out by the end of a project. Marketing and management could make educated estimates based on objective data about how their decisions would affect project schedules. Stakeholders (design, verification, marketing, management, firmware, software and applications) could know that their concerns with respect to design verification had been met.

Imagine an entire team agreeing on a set of concerns and priorities for a project with visibility into the verification process. Sounds pretty good doesn't it?

These capabilities would allow engineering and management to concentrate on the work at hand, knowing that the project is tracking well towards the ultimate goal of successful delivery. It would bestow upon each stakeholder the ability and the responsibility to alert the team if their concerns were not being addressed.

Best of all, heightened visibility would allow team members to issue project alerts when needed mostduring the execution of the project. Alerts could be issued the instant concerns begin to surface, not at the end of the project when their alert could only serve as a historical anecdote and a cautionary tale for future projects.

We also need to make sure team leaders and managers know what each team member is contributing toward successful completion of the project. Managers need to be aware of what the contribution level is, not just what it was supposed to be. This ability allows team leaders to detect issues early, so they can be corrected, or detect discrepancies between the estimated time to completion and the actual time being used. Management needs to detect misalignments as they emerge, not at the post-mortem meetings.

To be more productive, we also need to effectively manage the gigabytes of data produced by today's verification methodologies. This would allow users to determine which failed verification scenarios were the most effective for debug efforts, automatically determine the shortest scenario to be rerun or find all scenarios that contributed to a specific failure mechanism. This approach would permit examination of all scenarios that exercised a specific problematic portion of the device, but did not fail. Engineers would also be able to determine which parts of the verification task have been completed and then effectively focus on the next highest priority.

By using a methodology that features metric-driven process automation, much more can be accomplished. Here's a framework:

  • First, the team creates project based on need. They determine what the most important features of the device are and how to measure when those features have been effectively verified. Each stakeholder contributes their requirements early in the planning and participates by determining how to objectively measure that those requirements have been met.

  • A verification team then begins to execute on those requirements. As they implement the mechanisms to address each requirement, they also implement objective measurements, (functional coverage, code coverage, software coverage, assertion coverage) that indicate that requirements have been met. As the verification engines like simulation execute, they produce the measurements (metrics), specified.

  • These metrics are then collected by a metric-driven process automation and management solution and are made available, enabling the team to react and make changes based on real-time data. The same metrics can also be used to drive other automation engines that "react" to facilitate verification closure tracking, debug analysis, test scenario generation and other verification processes.

Ultimately, the project development loop is closed by making any necessary adjustments to the plan, like reprioritizations, reallocations or additional automated debug scenario executions to gain detailed insights into design failures. Since the loop is closed, the team also gets an ongoing indication of how well the overall objectives are being met, eliminating schedule "shocks" that lead to future market disruptions.

It is vital for design and verification teams to work together so that each team member can benefit from this new field that combines verification innovation and automated management. You can learn more about this framework in the upcoming book, "Metric Driven Verification: An Executive's and Engineer's Guide to First Pass Silicon Success," which details the framework and the infrastructure behind it.

About the author
Hamilton Carter
is senior technical leader for verification at Cadence Design Systems. He is the co-author, along with Shankar Hemmady, of "Metric Driven Verification: An Executive's and Engineer's Guide to First Pass Silicon Success."

Article Comments - Commentary: Imagination turns to rea...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top