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Telecom timing chip enables 1G, 10G SyncE

Posted: 23 Jul 2007 ?? ?Print Version ?Bookmark and Share

Keywords:Synchronous Ethernet line cards? wireless base stations? network synchronization?


Maxim Integrated Products claims that its DS3104 chip is the industry's first to provide full carrier-class clock synchronization for new Synchronous Ethernet (SyncE) line cards and mixed SONET/SDH/SyncE line cards. The new line-card timing IC utilizes Maxim's DSP-based digital PLL (DPLL) technology, first used in the DS3100 timing-card-on-a-chip IC, in this.

Key innovations in the DS3104 include two independent DPLLs for bidirectional frequency conversion between Ethernet clock rates and SONET/SDH rates and complete support for all 1G, 10G and 100M Ethernet MII clock rates. Applications include line cards and other subsystems in wireline and wireless systems, including ADMs, digital cross-connects, carrier-class switches and routers, wireless base stations, DSLAMs and multiservice access nodes.

Ethernet is seen to be gradually replacing PDH and SONET/SDH links in service-provider networks. Telecom service providers are thus challenged how to carry high-quality clock synchronization over Ethernet to serve several demanding applications including wireless base stations and TDM circuit emulation (CES) equipment. One recently standardized method to address this challenge is SyncE, in which Ethernet links are synchronized by timing their bit clocks from high-quality, stratum-1-traceable clock signals in exactly the same manner as SONET/SDH.

Architectural overview
DS3104 continually monitors up to eight input clocks. Built-in reference-selection logic automatically chooses the highest priority, valid input clock for each of the two DPLLs.

The main DPLL typically takes system clocks (such as 19.44MHz) from dual redundant timing cards, monitors both, selects one to which to lock and synthesizes various clocks needed on the line card (such as 125MHz for 1G SyncE transmitters). This main DPLL also provides the hitless switching and holdover capabilities needed on the line card. The second DPLL is typically used to convert recovered line clocks (such as 125MHz from 1G SyncE receivers) to suitable backplane line clocks (such as 19.44MHz), which are sent to the two system timing cards. Each DPLL is followed by a clock-multiplying, jitter-attenuating APLL and dividers that can provide a wide array of clock rates to the seven output clocks.

Technical details
The DS3104 chip has very flexible clock I/O capabilities. Eight clock inputs are available, and each can be assigned to either of the two internal DPLLs. Inputs are continually monitored for quality and can be automatically qualified and disqualified by the device according to configurable criteria. Four clock inputs are CMOS/TTL, the other four are LVDS/LVPECL or CMOS/TTL. The eight clock inputs accept all common telecom clock rates including 2kHz, 8kHz, DS1, E1, DS2, DS3, E3, OC-3 and Nx19.44MHz and all Ethernet MII clock rates including 25MHz, 125MHz and 156.25MHz. The clock inputs also accept all multiples of 2kHz up to 77.76MHz and all multiples of 8kHz up to 155.52MHz, making the inputs compatible with a variety of other industry clock rates including 13MHz and 30.72MHz base station clocks and 10MHz from GPS receivers.

The DPLLs in the DS3104 can direct-lock to a number of common telecom frequencies. The DPLLs can also lock to integer multiples of the direct-lock frequencies by using programmable input dividers. DPLL bandwidths are programmable from 1Hz to 600Hz, and a variety of damping factors are available. The main DPLL can optionally use phase build-out techniques to perform hitless switching to the secondary system clock when the primary system clock fails. Typical output-clock phase movement in this scenario is less than 1ns, even when the device is clocked by an inexpensive crystal oscillator, which is not temperature-compensated. The main DPLL also has a precise digital holdover mode to maintain output clocks in case both system clock references fail or are unavailable.

DS3104 can produce a total of seven output-clock frequencies simultaneously, plus 2kHz and 8kHz frame pulses. Each output clock can be frequency-locked to either of the two DPLLs for maximum flexibility. For combination SONET/SDH/SyncE line cards, the device can simultaneously produce SONET/SDH rates (such as 155.52MHz), the 1G Ethernet GMII clock rate (125MHz), and the 10G Ethernet XGMII clock rate (156.25MHz or 312.5MHz). All rates are frequency-locked to the selected system clock through the main DPLL. Of the seven output clocks, three are CMOS/TTL, two are LVDS/LVPECL and two are dual CMOS/TTL and LVDS/LVPECL. The output clocks have the same frequency options as the input clocks, plus differential-signal rates as high as 312.5MHz. Moreover, programmable synthesis engines can produce any multiple of 2kHz up to 77.76MHz, any multiple of 8kHz up to 311.04MHz and many other frequencies as needed.

The DS3104 ICs are available now. The device has an SPI serial bus interface and is packaged in an 81-lead, 10mm x 10mm BGA. Both 5/6- and full-RoHS-compliant package options are available. The device operates over the full industrial temperature range of -40C to 85C. Prices start at $33.60 (1,000-unit quantities). The DS3104DK demo kit is available for device evaluation.

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