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How to share IP in PCB design

Posted: 01 Aug 2007 ?? ?Print Version ?Bookmark and Share

Keywords:IP in PCB design? sharing IP? EDA tools for PCB design?

Historically, the design engineer has always envisioned the bus structure and its relationship with its components while designing and capturing logic. This envisioned structure is considered intellectual property (IP), typically a valuable asset to an organization. The problem is capturing and sharing this IP. This article discusses the disconnect between the digital designer's vision of bus structures on the PCB, and the failure of tools to capture and route this vision efficiently.

Often, design engineers attempt to capture and communicate IP in a hand-drawn document or on a paper napkin. While many aspects of EDA are automated, this process has not had effective tool support. A hand-drawing on a napkin has been the most efficient to date.

Although the napkin is quick to capture, it may or may not physically map to the PCB. This is a problem because of size issues such as the physical bus' width, the card's mechanical parameters, and the components' physical size and pinouts. Thus, the original IP may be completely invalid because it is physically impossible to follow. EDA tools must not only replace, but also improve on the napkin. They must effectively capture the IP and communicate accurate, usable/reusable IP throughout the design process.

When the IP is accurately captured, collaboration is required throughout the remaining design flow. Effective collaboration shortens the design timeframe by preventing the re-entry of IP by others. Additionally, by using the exact IP, the original intent is maintained. Errors and misunderstandings are removed with effective collaboration, with the result being increased efficiency in the design flow.

Bus structure
A topology planning tool is needed. This tool should allow the design engineer to define and capture the bus structure and effectively communicate it throughout the design flow. To effectively plan bus structures, they must first be logically defined. Bus definitions can come forward from captured logic in the schematic or ASCII input, depending on the design flow. With buses defined, a card outline, components and board stackup, the design is ready for accurate capture of the topology.

The tools to capture topology must be easy to use, flexible and accurate while providing useful visual feedback. This should start with a true, exact physical representation of bus paths. A 64bit bus must truly represent the width of 64 parallel traces and 63 trace-to-trace clearances, all while understanding impedance implications per layer. Also, as buses are drawn on different layers, they need to be visually represented on these layers. The purpose is to ensure that what the design engineer is capturing actually fits into the sections of the PCB where they're intended to. Otherwise, the integrity of the IP is in jeopardy.

Design engineers must be flexible when creating their IP, and they should be able to draw their bus paths with a few key components placed, all components placed or no components placed. A topology planning tool should aid in the creation process by providing flexibility, not force a procedure.

Since the placement of components affects the bus structure and vice versa, efficient topology planning must support the placement of components by buses. During placement, designers should be able to filter and place those components that share a bus. The selection of a bus should filter the component list to include components associated with the selected bus.

When placing components, it's typical that net lines span between component pins and aid in placing. This provides a useful purpose, real-time feedback of component connections to associated components. Yet, as more components are placed, more net lines are brought into the display. For complex designs, the density, overlapping and twisting of net lines can cause more confusion than guidance.

The two parts of the figure show a general flow of interconnects between components. Effective topology planning tools must provide a better understanding of relationship between buses and their components by showing net lines funneling into bus paths.

Topology planning benefit
In the figure, both displays are useful while capturing IP. Yet the evolved image in the right shows the organization and visual benefit brought through topology planning. Net-lines are bundled in their layer-specific paths, showing accurate space requirements. The results are a clear representation of bus-to-component relationships while understanding scale. As they draw their bus paths, design engineers create order in the placement and are able to visually see and dictate how the bus is routed and components placed.

Bus paths may accommodate any count of bits up to the total defined in the bus. This provides great flexibility in planning the bus structures. Topology planning must include optional abilities to capture complex bus structures to include: layer changes with via patterns, T-junctions, V and T splits, net-lines spanning from the sides of bus paths, overlapping paths of same bus, and net line assignments with bit ordering.

Although flexible, a "packed" bus structure does not work with all topology planning scenarios. If, for example, there are two BGAs close together sharing a 64bit bus, there may not be enough room for a packed bus path. In this scenario, it is better to go with an unpacked area for the bus. An unpacked area doesn't dictate a packed structureinstead, it specifies layers, layer bias per selected layer and area for the selected bus bits to route. The engineer still captures IP, but with an area border, layers and layer bias.

Timing concerns create signal delays that can consume a lot of trace space on a PCB. Rather than being surprised to where they'll fit, it's best to estimate the needed space and plan where tune delay lengths will be added.

A good topology planning tool provides this capability, where it's needed during the planning stage, allowing the design engineer to specify areas on the PCB to locate the delay lengths. Planning ahead of the process ensures that the needed space is available. A plan should also be able to manage and specify the area for signal delay traces.

SI problems
With ever increasing signal frequencies, it is crucial to consider signal integrity during topology planning. Planning for signal integrity includes insuring against crosstalk, parallelism and planning for return signal path. Typical design flows find SI problems after most traces are routed and the design almost complete.

Depending on the SI problem, the solution may require space between signal traces or a ground shield between the two signal traces, or a ground/voltage plane clear of obstacles. Yet the PCB design is almost complete and may have high trace density in the area of the PCB where the problems are occurring. This is the wrong time in the design cycle to be informed of SI problems because there may not be enough physical space to easily solve the problem.

Topology planning is the right time to plan for signal integrity, before traces are committed to the PCB. Instead of trying to find space after the interconnects are completed, it is better to plan for a return path, prevent crosstalk and parallelism before trace routing is started. Otherwise, the necessary space for a plane layer, spacer or ground shielding may be unavailable. If planned for, instead of reacting to SI issues, the design cycle is further shortened by anticipating these potential problems early and necessary signal performance is achieved.

- Dean Wiltshire
Product Architect, System Design Division
Mentor Graphics Corp.

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