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Follow a balanced DFx flow

Posted: 01 Aug 2007 ?? ?Print Version ?Bookmark and Share

Keywords:interconnect design challenges? interconnect optimization? DFx flow design?

In moving to advanced process technologies, IC companies face growing pressure to achieve first-time silicon success despite a growing array of manufacturing requirements. Fabs expect designs to conform to increasingly complex rules and recommendations for design-for-manufacturing (DFM) and design-for-yield (DFY) at advanced process nodes. For their part, designers look to maximize performance while minimizing guardbanding.

Increased manufacturing complexity presents growing difficulties in creating vias, dealing with closely packed wires and handling the increased effects of nanometer geometries. Because of these growing interconnect design challenges, semiconductor companies face typical yields of 40-70 percent for advanced process nodestranslating into millions of dollars lost in yield alone. For IC design teams, these increased demands dictate a more collaborative approach. Indeed, both design and manufacturing can find mutual benefit from the latest optimization methods for "DFx" (DFM, DFY and design-for-reliability).

This balanced approach to interconnect optimization following conventional place and route flows can improve yield, manufacturability and timing closure during design while addressing electrical constraints and manufacturing rules.

The best DFx flow available today combines the DFM-aware features in today's synthesis, placement and routing solutions with a post-route (pre-GDS) interconnect optimization step.


  • Be sure to incorporate design intent, such as critical net information, to avoid SI and timing issues after DFx enhancements. In particular, protect critical nets by locking them and creating a protection halo around them. The halo can be represented as a conservative "keep out" spacing value for the same layer or the full layer stack.

  • Perform electrically aware/correct analysis during DFx enhancements to ensure that timing and signal integrity are not being violated. This approach enables convergence after the DFx optimizations and ensures that the design isn't over-guardbanded earlier in the flow.

  • Properly sequence the DFx enhancements. Proper sequencing will help produce optimal results, because each step will facilitate the following step. For example, start with a timing/SI and DRC clean block, then apply via reduction techniques, followed by wire spreading, redundancy via insertion and enclosure enhancements.

  • Treat DFx closure just as you treat timing closure. Do it early in the design cycle and for each block. If possible, add DFx to the entire flow. Cell yield can be addressed early in the flow during synthesis and placement. Interconnects can be made more friendly for lithography, optical proximity correction and DFx while routing. And finally, using advanced methods such as space-based modeling, further DFx and lithography enhancements can be made on the routed data.

  • Perform optimal DFx enhancements by using next-generation methods such as space-based tools that aren't restricted by grids.


  • Underestimate the importance of interconnect optimization. Besides reducing guardbanding and improving chip performance, it can offer measurable benefits in speeding ramp to volume and even improving yield by up to 6 percentage points. One point-of-yield improvement translates into millions of dollars of savings, and faster time-to-volume can profoundly affect revenue.

  • Take a narrow view in measuring and scoring the improvements. For example, if vias are a source of reliability and manufacturability problems, don't just count double-cuts; look at the total number of protected and unprotected vias. Protected vias are defined as redundant vias or those with better enclosures. Compare total protected and unprotected vias in the original design with the total protected and unprotected vias in the optimized design.

  • Assume that any fab or even any process node is the same as the others. Each fab and process node is different. For example, the probability of metal shorts vs. opens varies by material (aluminum vs. copper) and process node. Set aside enough time to evaluate the effectiveness of the previous DFx flow on the new process.

  • Treat a fab's recommended rules as merely optional. Work with the fab to determine the list of top yield detractors. Attempt to abide by those rules, violating them only if design (e.g. timing and power) or area objectives are not being met. Incorporate a checking/scoring mechanism to see how well you are doing against the recommended rules.

  • Do all your DFx enhancements on GDS data. Only a limited set of geometric enhancements can be done at this stage. You can best optimize your DFx enhancements by performing them prior to GDS and using a tool that can perform topological optimizations.

- Wilbur Luo
Product Director, Cadence Design Systems Inc.

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