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Virtex-5 FPGAS are interoperable with 800Mbps DDR3

Posted: 03 Aug 2007 ?? ?Print Version ?Bookmark and Share

Keywords:FPGA controller Virtex-5 FPGA? signal integrity? reference design?

Xilinx Inc. claims that its Virtex-5 FPGA devices are now interoperable with 800Mbps DDR3 SDRAM devices from leading memory suppliers. Hardware-proven interoperability with Virtex-5 devices provides customers with an early path to adopt DDR3 SDRAM technology with the high-performance 65nm FPGA family.

Successful interoperability hardware tests were performed using devices from leading memory manufacturers, Micron Technology Inc. and Elpida Memory Inc. Xilinx enables designers to begin their designs today by offering DDR3 SDRAM support in its Virtex-5 LXT ML561 FPGA Advanced Memory Interfaces Tool Kit, which is shipping today.

"Elpida and Xilinx have strategically partnered to enable new DRAM technologies in markets requiring high performance and cost effective solutions," said Bijan Yazdani, VP of sales at Elpida Memory. "Through successful DDR3 and Virtex-5 FPGA interoperability testing, Xilinx will provide their customers with the first hardware verified FPGA controller for faster proliferation of DDR3 DRAM technology."

The DDR3 SDRAM architecture, as an evolutionary step from DDR2 SDRAM, provides increased bandwidth, lower power consumption (1.5V vs. 1.8V power supply for DDR2 SDRAM) and improved I/O signaling for better signal integrity to enable higher system performance.

The interoperability tests performed on the Virtex-5 LXT ML561 FPGA Advanced Memory Interfaces Tool Kit verified a DDR3 SDRAM controller and interface reference design that is scheduled to be made broadly available in September. The reference design leverages Virtex-5 FPGA features like the IODELAY, a programmable input and output delay block that ensures accuracy of read data capture and configurable write data signals to achieve 800Mbps data rates and DDR3 SDRAM functional requirements.

The Virtex-5 LXT ML561 FPGA Advanced Memory Interfaces Tool Kit with DDR3 SDRAM interface is available today for $5,995. The ML561 can also be used to evaluate DDR2 SDRAM, DDR SDRAM, QDR II SRAM and RLDRAM II interfaces. Complete DDR3 hardware proven reference design files are available for free download from Xilinx in September.




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