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Xilinx provides free reference design for DDR2-400

Posted: 09 Aug 2007 ?? ?Print Version ?Bookmark and Share

Keywords:DDR2 SDRAM interface? DDR2-400? FPGAs? reference design?

Xilinx Inc. has announced support for a 400Mbps DDR2 SDRAM interface (DDR2-400) with its low-cost 90nm Spartan-3A and Spartan-3AN FPGAs. Designers can download a free hardware-verified reference design providing quick implementation of a 400Mbps DDR2 SDRAM interface. The reference design complements the company's comprehensive suite of development kits and software tools offered to assist customers in memory interface implementations. DDR2 SDRAM interfaces are widely used in applications such as low-cost video and networking.

"The development of HDTV and its requirement for low-cost, high-memory bandwidth has created demand for high performance DDR2 memory interfaces. By providing a solution based on our high-volume Spartan-3A and Spartan-3AN FPGAs available now, designers can implement a variety of high-resolution video or graphic frame buffers," said Oliver Garreau, senior manager of applications engineering, general products division at Xilinx. "Our customers can now leverage a fully-verified DDR2-400 reference design and low-cost development kits to move their design to production faster."

The 400Mbps DDR2 memory interface reference design, including data capture circuitry and memory controller, is fully verified in hardware using Xilinx Spartan-3A FPGA high speed grade (-5) devices. The hardware validation process was completed using a Spartan-3A FPGA Starter Kit board with (-5) devices which includes full characterization at different process corners, as well as temperature and voltage variations that meet commercial grade requirements.

Xilinx also offers a Memory Interface Generator (MIG) for ultimate design flexibility and ease-of-use. The MIG is a free, user-friendly parameterizable software tool designed to create memory interface designs in unencrypted RTL. MIG supports multiple memory architectures, device and package combinations that provide system designers with the flexibility to easily customize their own design. MIG is integrated in the Xilinx CORE Generator software and provides RTL source and constraints files through a graphical interface for ultimate user flexibility.

The free 400Mbps DDR2 SDRAM interface reference design for Spartan-3A and Spartan-3AN FPGAs, including graphic demo files, is available for immediate download at

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